arm64: dts: ti: k3-j784s4: Add Wave5 Video Encoder/Decoder Node

This patch adds support for the Wave521cl on the J784S4-evm.

Signed-off-by: Brandon Brnich <b-brnich@ti.com>
Link: https://lore.kernel.org/r/20240220191413.3355007-2-b-brnich@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>

diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
index c83f337d2f35fc43b4fb168100b1f040e58873d0..b67c37460a73d8033107ded849b3b445e49d7d35 100644 (file)
--- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi
@@ -844,6 +844,22 @@
                status = "disabled";
        };
 
+       vpu0: video-codec@4210000 {
+               compatible = "ti,j721s2-wave521c", "cnm,wave521c";
+               reg = <0x00 0x4210000 0x00 0x10000>;
+               interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&k3_clks 241 2>;
+               power-domains = <&k3_pds 241 TI_SCI_PD_EXCLUSIVE>;
+       };
+
+       vpu1: video-codec@4220000 {
+               compatible = "ti,j721s2-wave521c", "cnm,wave521c";
+               reg = <0x00 0x4220000 0x00 0x10000>;
+               interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&k3_clks 242 2>;
+               power-domains = <&k3_pds 242 TI_SCI_PD_EXCLUSIVE>;
+       };
+
        main_sdhci0: mmc@4f80000 {
                compatible = "ti,j721e-sdhci-8bit";
                reg = <0x00 0x04f80000 0x00 0x1000>,

diff --git a/arch/arm64/boot/dts/ti/k3-j784s4.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4.dtsi
index 271a217905e94b62d7c83a11d68061bea3676606..6e2e92ffe7452b8a8ed1c1ece3b451a6360dceec 100644 (file)
--- a/arch/arm64/boot/dts/ti/k3-j784s4.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j784s4.dtsi
@@ -235,6 +235,8 @@
                ranges = <0x00 0x00100000 0x00 0x00100000 0x00 0x00020000>, /* ctrl mmr */
                         <0x00 0x00600000 0x00 0x00600000 0x00 0x00031100>, /* GPIO */
                         <0x00 0x01000000 0x00 0x01000000 0x00 0x0d000000>, /* Most peripherals */
+                        <0x00 0x04210000 0x00 0x04210000 0x00 0x00010000>, /* VPU0 */
+                        <0x00 0x04220000 0x00 0x04220000 0x00 0x00010000>, /* VPU1 */
                         <0x00 0x0d000000 0x00 0x0d000000 0x00 0x01000000>, /* PCIe Core*/
                         <0x00 0x10000000 0x00 0x10000000 0x00 0x08000000>, /* PCIe0 DAT0 */
                         <0x00 0x18000000 0x00 0x18000000 0x00 0x08000000>, /* PCIe1 DAT0 */