docs: sh: convert register-banks.txt to ReST

- Add a SPDX header;
- Adjust document title to follow ReST style;
- Add blank lines to make ReST markup happy
- Add it to sh/index.rst.

Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
Link: https://lore.kernel.org/r/adf117cf1edd7f43cb839ff2800f4315dfbcce13.1592203650.git.mchehab+huawei@kernel.org
Signed-off-by: Jonathan Corbet <corbet@lwn.net>

diff --git a/Documentation/sh/index.rst b/Documentation/sh/index.rst
index 967acad9ff5e9968f9a23df069f7d331e8ed3afc..b5933fd399f3be16a64492ae9c67f7d254a6f299 100644 (file)
--- a/Documentation/sh/index.rst
+++ b/Documentation/sh/index.rst
@@ -8,6 +8,7 @@ SuperH Interfaces Guide
     :maxdepth: 1
 
     new-machine
+    register-banks
 
 Memory Management
 =================

diff --git a/Documentation/sh/register-banks.rst b/Documentation/sh/register-banks.rst
new file mode 100644 (file)
index 0000000..2bef5c8
--- /dev/null
+++ b/Documentation/sh/register-banks.rst
@@ -0,0 +1,40 @@
+.. SPDX-License-Identifier: GPL-2.0
+
+==========================================
+Notes on register bank usage in the kernel
+==========================================
+
+Introduction
+------------
+
+The SH-3 and SH-4 CPU families traditionally include a single partial register
+bank (selected by SR.RB, only r0 ... r7 are banked), whereas other families
+may have more full-featured banking or simply no such capabilities at all.
+
+SR.RB banking
+-------------
+
+In the case of this type of banking, banked registers are mapped directly to
+r0 ... r7 if SR.RB is set to the bank we are interested in, otherwise ldc/stc
+can still be used to reference the banked registers (as r0_bank ... r7_bank)
+when in the context of another bank. The developer must keep the SR.RB value
+in mind when writing code that utilizes these banked registers, for obvious
+reasons. Userspace is also not able to poke at the bank1 values, so these can
+be used rather effectively as scratch registers by the kernel.
+
+Presently the kernel uses several of these registers.
+
+       - r0_bank, r1_bank (referenced as k0 and k1, used for scratch
+         registers when doing exception handling).
+
+       - r2_bank (used to track the EXPEVT/INTEVT code)
+
+               - Used by do_IRQ() and friends for doing irq mapping based off
+                 of the interrupt exception vector jump table offset
+
+       - r6_bank (global interrupt mask)
+
+               - The SR.IMASK interrupt handler makes use of this to set the
+                 interrupt priority level (used by local_irq_enable())
+
+       - r7_bank (current)

diff --git a/Documentation/sh/register-banks.txt b/Documentation/sh/register-banks.txt
deleted file mode 100644 (file)
index a6719f2..0000000
--- a/Documentation/sh/register-banks.txt
+++ /dev/null
@@ -1,33 +0,0 @@
-       Notes on register bank usage in the kernel
-       ==========================================
-
-Introduction
-------------
-
-The SH-3 and SH-4 CPU families traditionally include a single partial register
-bank (selected by SR.RB, only r0 ... r7 are banked), whereas other families
-may have more full-featured banking or simply no such capabilities at all.
-
-SR.RB banking
--------------
-
-In the case of this type of banking, banked registers are mapped directly to
-r0 ... r7 if SR.RB is set to the bank we are interested in, otherwise ldc/stc
-can still be used to reference the banked registers (as r0_bank ... r7_bank)
-when in the context of another bank. The developer must keep the SR.RB value
-in mind when writing code that utilizes these banked registers, for obvious
-reasons. Userspace is also not able to poke at the bank1 values, so these can
-be used rather effectively as scratch registers by the kernel.
-
-Presently the kernel uses several of these registers.
-
-       - r0_bank, r1_bank (referenced as k0 and k1, used for scratch
-         registers when doing exception handling).
-       - r2_bank (used to track the EXPEVT/INTEVT code)
-               - Used by do_IRQ() and friends for doing irq mapping based off
-                 of the interrupt exception vector jump table offset
-       - r6_bank (global interrupt mask)
-               - The SR.IMASK interrupt handler makes use of this to set the
-                 interrupt priority level (used by local_irq_enable())
-       - r7_bank (current)
-

diff --git a/arch/sh/Kconfig.cpu b/arch/sh/Kconfig.cpu
index 97ca35f2cd37382b59ea793ea972c132c0fc5397..fff419f3d7574c16e5f965559ad98d449d5180f1 100644 (file)
--- a/arch/sh/Kconfig.cpu
+++ b/arch/sh/Kconfig.cpu
@@ -85,7 +85,7 @@ config CPU_HAS_SR_RB
          that are lacking this bit must have another method in place for
          accomplishing what is taken care of by the banked registers.
 
-         See <file:Documentation/sh/register-banks.txt> for further
+         See <file:Documentation/sh/register-banks.rst> for further
          information on SR.RB and register banking in the kernel in general.
 
 config CPU_HAS_PTEAEX