ARM: dts: Configure interconnect target module for dra7 pcie

We can now probe devices with device tree only configuration using
ti-sysc interconnect target module driver. Let's configure the
module, but keep the legacy "ti,hwmods" peroperty to avoid new boot
time warnings. The legacy property will be removed in later patches
together with the legacy platform data.

Tested-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>

diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index 39614c7232bf67237dac9ef5bece75a7e3f425a1..f7e40227d7de490c118317883339579ec4aae691 100644 (file)
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -166,8 +166,21 @@
                l4_per3: interconnect@48800000 {
                };
 
-               axi@0 {
-                       compatible = "simple-bus";
+               /*
+                * Register access seems to have complex dependencies and also
+                * seems to need an enabled phy. See the TRM chapter for "Table
+                * 26-678. Main Sequence PCIe Controller Global Initialization"
+                * and also dra7xx_pcie_probe().
+                */
+               axi0: target-module@51000000 {
+                       compatible = "ti,sysc-omap4", "ti,sysc";
+                       power-domains = <&prm_l3init>;
+                       resets = <&prm_l3init 0>;
+                       reset-names = "rstctrl";
+                       clocks = <&pcie_clkctrl DRA7_PCIE_PCIE1_CLKCTRL 0>,
+                                <&pcie_clkctrl DRA7_PCIE_PCIE1_CLKCTRL 9>,
+                                <&pcie_clkctrl DRA7_PCIE_PCIE1_CLKCTRL 10>;
+                       clock-names = "fck", "phy-clk", "phy-clk-div";
                        #size-cells = <1>;
                        #address-cells = <1>;
                        ranges = <0x51000000 0x51000000 0x3000>,
@@ -229,8 +242,21 @@
                        };
                };
 
-               axi@1 {
-                       compatible = "simple-bus";
+               /*
+                * Register access seems to have complex dependencies and also
+                * seems to need an enabled phy. See the TRM chapter for "Table
+                * 26-678. Main Sequence PCIe Controller Global Initialization"
+                * and also dra7xx_pcie_probe().
+                */
+               axi1: target-module@51800000 {
+                       compatible = "ti,sysc-omap4", "ti,sysc";
+                       clocks = <&pcie_clkctrl DRA7_PCIE_PCIE2_CLKCTRL 0>,
+                                <&pcie_clkctrl DRA7_PCIE_PCIE2_CLKCTRL 9>,
+                                <&pcie_clkctrl DRA7_PCIE_PCIE2_CLKCTRL 10>;
+                       clock-names = "fck", "phy-clk", "phy-clk-div";
+                       power-domains = <&prm_l3init>;
+                       resets = <&prm_l3init 1>;
+                       reset-names = "rstctrl";
                        #size-cells = <1>;
                        #address-cells = <1>;
                        ranges = <0x51800000 0x51800000 0x3000>,