arm64: tegra: Add NVDEC to Tegra186/194 device trees

Add a device tree node for NVDEC on Tegra186, and
device tree nodes for NVDEC and NVDEC1 on Tegra194.

Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
index e94f8add1a4001158e80c8ecbe45cef7dbe0b0e6..065185bd65edc3d3c703f96d38fe505b70bea0f5 100644 (file)
--- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
@@ -1433,6 +1433,22 @@
                        power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>;
                };
 
+               nvdec@15480000 {
+                       compatible = "nvidia,tegra186-nvdec";
+                       reg = <0x15480000 0x40000>;
+                       clocks = <&bpmp TEGRA186_CLK_NVDEC>;
+                       clock-names = "nvdec";
+                       resets = <&bpmp TEGRA186_RESET_NVDEC>;
+                       reset-names = "nvdec";
+
+                       power-domains = <&bpmp TEGRA186_POWER_DOMAIN_NVDEC>;
+                       interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVDECSRD &emc>,
+                                       <&mc TEGRA186_MEMORY_CLIENT_NVDECSRD1 &emc>,
+                                       <&mc TEGRA186_MEMORY_CLIENT_NVDECSWR &emc>;
+                       interconnect-names = "dma-mem", "read-1", "write";
+                       iommus = <&smmu TEGRA186_SID_NVDEC>;
+               };
+
                sor0: sor@15540000 {
                        compatible = "nvidia,tegra186-sor";
                        reg = <0x15540000 0x10000>;

diff --git a/arch/arm64/boot/dts/nvidia/tegra194.dtsi b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
index 5fc77b9667667e8f7d4965ee89c4242e95e34ebb..08513902a07052abc9b54ab6b93867ddd0b9192f 100644 (file)
--- a/arch/arm64/boot/dts/nvidia/tegra194.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra194.dtsi
@@ -1457,6 +1457,25 @@
                        interconnect-names = "dma-mem";
                        iommus = <&smmu TEGRA194_SID_HOST1X>;
 
+                       nvdec@15140000 {
+                               compatible = "nvidia,tegra194-nvdec";
+                               reg = <0x15140000 0x00040000>;
+                               clocks = <&bpmp TEGRA194_CLK_NVDEC1>;
+                               clock-names = "nvdec";
+                               resets = <&bpmp TEGRA194_RESET_NVDEC1>;
+                               reset-names = "nvdec";
+
+                               power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVDECB>;
+                               interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDEC1SRD &emc>,
+                                               <&mc TEGRA194_MEMORY_CLIENT_NVDEC1SRD1 &emc>,
+                                               <&mc TEGRA194_MEMORY_CLIENT_NVDEC1SWR &emc>;
+                               interconnect-names = "dma-mem", "read-1", "write";
+                               iommus = <&smmu TEGRA194_SID_NVDEC1>;
+                               dma-coherent;
+
+                               nvidia,host1x-class = <0xf5>;
+                       };
+
                        display-hub@15200000 {
                                compatible = "nvidia,tegra194-display";
                                reg = <0x15200000 0x00040000>;
@@ -1570,6 +1589,25 @@
                                iommus = <&smmu TEGRA194_SID_VIC>;
                        };
 
+                       nvdec@15480000 {
+                               compatible = "nvidia,tegra194-nvdec";
+                               reg = <0x15480000 0x00040000>;
+                               clocks = <&bpmp TEGRA194_CLK_NVDEC>;
+                               clock-names = "nvdec";
+                               resets = <&bpmp TEGRA194_RESET_NVDEC>;
+                               reset-names = "nvdec";
+
+                               power-domains = <&bpmp TEGRA194_POWER_DOMAIN_NVDECA>;
+                               interconnects = <&mc TEGRA194_MEMORY_CLIENT_NVDECSRD &emc>,
+                                               <&mc TEGRA194_MEMORY_CLIENT_NVDECSRD1 &emc>,
+                                               <&mc TEGRA194_MEMORY_CLIENT_NVDECSWR &emc>;
+                               interconnect-names = "dma-mem", "read-1", "write";
+                               iommus = <&smmu TEGRA194_SID_NVDEC>;
+                               dma-coherent;
+
+                               nvidia,host1x-class = <0xf0>;
+                       };
+
                        dpaux0: dpaux@155c0000 {
                                compatible = "nvidia,tegra194-dpaux";
                                reg = <0x155c0000 0x10000>;