gen9_dbuf_enable(dev_priv);
- if (resume && intel_dmc_has_payload(dev_priv))
+ if (resume)
intel_dmc_load_program(dev_priv);
}
gen9_dbuf_enable(dev_priv);
- if (resume && intel_dmc_has_payload(dev_priv))
+ if (resume)
intel_dmc_load_program(dev_priv);
}
if (IS_DG2(dev_priv))
intel_snps_phy_wait_for_calibration(dev_priv);
- if (resume && intel_dmc_has_payload(dev_priv))
+ if (resume)
intel_dmc_load_program(dev_priv);
/* Wa_14011508470:tgl,dg1,rkl,adl-s,adl-p */
struct intel_dmc *dmc = &dev_priv->dmc;
u32 id, i;
- if (!HAS_DMC(dev_priv)) {
- drm_err(&dev_priv->drm,
- "No DMC support available for this platform\n");
- return;
- }
-
- if (!dev_priv->dmc.dmc_info[DMC_FW_MAIN].payload) {
- drm_err(&dev_priv->drm,
- "Tried to program CSR with empty payload\n");
+ if (!intel_dmc_has_payload(dev_priv))
return;
- }
assert_rpm_wakelock_held(&dev_priv->runtime_pm);