drm/amdgpu: resize VRAM BAR for CPU access on gfx10
authorAlan Swanson <reiver@improbability.net>
Thu, 21 May 2020 20:29:30 +0000 (21:29 +0100)
committerAlex Deucher <alexander.deucher@amd.com>
Thu, 21 May 2020 22:00:01 +0000 (18:00 -0400)
Try to resize BAR0 to let CPU access all of VRAM on Navi. Syncs
code with previous gfx generations from commit d6895ad39f3b39
("drm/amdgpu: resize VRAM BAR for CPU access v6").

Signed-off-by: Alan Swanson <reiver@improbability.net>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c

index edaa50d850a6ade0ca3689ae195c868c71fa410a..ba2b7ac0c02da0af321117e2ce5ec7109e383af8 100644 (file)
@@ -686,17 +686,23 @@ static void gmc_v10_0_vram_gtt_location(struct amdgpu_device *adev,
  */
 static int gmc_v10_0_mc_init(struct amdgpu_device *adev)
 {
-       /* Could aper size report 0 ? */
-       adev->gmc.aper_base = pci_resource_start(adev->pdev, 0);
-       adev->gmc.aper_size = pci_resource_len(adev->pdev, 0);
+       int r;
 
        /* size in MB on si */
        adev->gmc.mc_vram_size =
                adev->nbio.funcs->get_memsize(adev) * 1024ULL * 1024ULL;
        adev->gmc.real_vram_size = adev->gmc.mc_vram_size;
-       adev->gmc.visible_vram_size = adev->gmc.aper_size;
+
+       if (!(adev->flags & AMD_IS_APU)) {
+               r = amdgpu_device_resize_fb_bar(adev);
+               if (r)
+                       return r;
+       }
+       adev->gmc.aper_base = pci_resource_start(adev->pdev, 0);
+       adev->gmc.aper_size = pci_resource_len(adev->pdev, 0);
 
        /* In case the PCI BAR is larger than the actual amount of vram */
+       adev->gmc.visible_vram_size = adev->gmc.aper_size;
        if (adev->gmc.visible_vram_size > adev->gmc.real_vram_size)
                adev->gmc.visible_vram_size = adev->gmc.real_vram_size;