drm/msm/dpu: fix writeback programming for YUV cases

For YUV cases, setting the required format bits was missed
out in the register programming. Lets fix it now in preparation
of adding YUV formats support for writeback.

changes in v2:
    - dropped the fixes tag as its not a fix but adding
      new functionality

Signed-off-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/571814/
Link: https://lore.kernel.org/r/20231212205254.12422-4-quic_abhinavk@quicinc.com
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c
index 9ca41de5ff7b62d8082f5e3edd60f5bdcae37df8..c6e9c11b6971d0094e87d1a77345f3e8c5b0a4df 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c
@@ -272,7 +272,6 @@ static int dpu_encoder_phys_wb_atomic_check(
 {
        struct drm_framebuffer *fb;
        const struct drm_display_mode *mode = &crtc_state->mode;
-       int ret;
 
        DPU_DEBUG("[atomic_check:%d, \"%s\",%d,%d]\n",
                        phys_enc->hw_wb->idx, mode->name, mode->hdisplay, mode->vdisplay);

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c
index ed0e80616129a6ff39b72109d2869990d08d2ef3..e75995f7fcea9635bb816929a37e583a91ac5aac 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c
@@ -89,6 +89,9 @@ static void dpu_hw_wb_setup_format(struct dpu_hw_wb *ctx,
                        dst_format |= BIT(14); /* DST_ALPHA_X */
        }
 
+       if (DPU_FORMAT_IS_YUV(fmt))
+               dst_format |= BIT(15);
+
        pattern = (fmt->element[3] << 24) |
                (fmt->element[2] << 16) |
                (fmt->element[1] << 8)  |