drm/xe/sr: Apply masked registers properly

The 'clear' field for register save/restore entries was being placed in
the value bits of the register rather than the mask bits; make sure it
gets shifted into the mask bits.

Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Matt Atwood <matthew.s.atwood@intel.com>
Reviewed-by: Matt Atwood <matthew.s.atwood@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Link: https://lore.kernel.org/r/20230419224909.4000920-1-matthew.d.roper@intel.com
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

diff --git a/drivers/gpu/drm/xe/xe_reg_sr.c b/drivers/gpu/drm/xe/xe_reg_sr.c
index ff83da4cf4a76a085807d66e07519ef6bf9d240b..e38397fc771a12406a279758745c6482dd617c53 100644 (file)
--- a/drivers/gpu/drm/xe/xe_reg_sr.c
+++ b/drivers/gpu/drm/xe/xe_reg_sr.c
@@ -148,7 +148,7 @@ static void apply_one_mmio(struct xe_gt *gt, u32 reg,
         * supposed to set all bits.
         */
        if (entry->masked_reg)
-               val = (entry->clr_bits ?: entry->set_bits << 16);
+               val = (entry->clr_bits ?: entry->set_bits) << 16;
        else if (entry->clr_bits + 1)
                val = (entry->reg_type == XE_RTP_REG_MCR ?
                       xe_gt_mcr_unicast_read_any(gt, MCR_REG(reg)) :