arm64: dts: ti: k3-j721e: correct cache-sets info

A72 Cluster has 48KB Icache, 32KB Dcache and 1MB L2 Cache
 - ICache is 3-way set-associative
 - Dcache is 2-way set-associative
 - Line size are 64bytes

So correct the cache-sets info.

Fixes: 2d87061e70dea ("arm64: dts: ti: Add Support for J721E SoC")
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Link: https://lore.kernel.org/r/20211112063155.3485777-1-peng.fan@oss.nxp.com

diff --git a/arch/arm64/boot/dts/ti/k3-j721e.dtsi b/arch/arm64/boot/dts/ti/k3-j721e.dtsi
index 214359e7288b23c1326c76e5c047d883298fb3d4..a5967ba139d7e3db78347da0c52b79dd56c204d4 100644 (file)
--- a/arch/arm64/boot/dts/ti/k3-j721e.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721e.dtsi
@@ -64,7 +64,7 @@
                        i-cache-sets = <256>;
                        d-cache-size = <0x8000>;
                        d-cache-line-size = <64>;
-                       d-cache-sets = <128>;
+                       d-cache-sets = <256>;
                        next-level-cache = <&L2_0>;
                };
 
@@ -78,7 +78,7 @@
                        i-cache-sets = <256>;
                        d-cache-size = <0x8000>;
                        d-cache-line-size = <64>;
-                       d-cache-sets = <128>;
+                       d-cache-sets = <256>;
                        next-level-cache = <&L2_0>;
                };
        };