dmaengine: xilinx: xdma: Add necessary macro definitions

Complete lacking bits describing the status/control register values.
Add macros describing the status/control registers.

Signed-off-by: Jan Kuliga <jankul@alatek.krakow.pl>
Link: https://lore.kernel.org/r/20231218113943.9099-3-jankul@alatek.krakow.pl
Signed-off-by: Vinod Koul <vkoul@kernel.org>

diff --git a/drivers/dma/xilinx/xdma-regs.h b/drivers/dma/xilinx/xdma-regs.h
index 0b17a931f58307f1cd0226bab231160f54afc3b3..98117e8a466fa2c97e0bdfde24b1a550acf535e7 100644 (file)
--- a/drivers/dma/xilinx/xdma-regs.h
+++ b/drivers/dma/xilinx/xdma-regs.h
@@ -76,6 +76,7 @@ struct xdma_hw_desc {
 #define XDMA_CHAN_CONTROL_W1S          0x8
 #define XDMA_CHAN_CONTROL_W1C          0xc
 #define XDMA_CHAN_STATUS               0x40
+#define XDMA_CHAN_STATUS_RC            0x44
 #define XDMA_CHAN_COMPLETED_DESC       0x48
 #define XDMA_CHAN_ALIGNMENTS           0x4c
 #define XDMA_CHAN_INTR_ENABLE          0x90
@@ -101,6 +102,7 @@ struct xdma_hw_desc {
 #define CHAN_CTRL_IE_MAGIC_STOPPED             BIT(4)
 #define CHAN_CTRL_IE_IDLE_STOPPED              BIT(6)
 #define CHAN_CTRL_IE_READ_ERROR                        GENMASK(13, 9)
+#define CHAN_CTRL_IE_WRITE_ERROR               GENMASK(18, 14)
 #define CHAN_CTRL_IE_DESC_ERROR                        GENMASK(23, 19)
 #define CHAN_CTRL_NON_INCR_ADDR                        BIT(25)
 #define CHAN_CTRL_POLL_MODE_WB                 BIT(26)
@@ -111,8 +113,17 @@ struct xdma_hw_desc {
                         CHAN_CTRL_IE_DESC_ALIGN_MISMATCH |             \
                         CHAN_CTRL_IE_MAGIC_STOPPED |                   \
                         CHAN_CTRL_IE_READ_ERROR |                      \
+                        CHAN_CTRL_IE_WRITE_ERROR |                     \
                         CHAN_CTRL_IE_DESC_ERROR)
 
+#define XDMA_CHAN_STATUS_MASK CHAN_CTRL_START
+
+#define XDMA_CHAN_ERROR_MASK (CHAN_CTRL_IE_DESC_ALIGN_MISMATCH |       \
+                             CHAN_CTRL_IE_MAGIC_STOPPED |              \
+                             CHAN_CTRL_IE_READ_ERROR |                 \
+                             CHAN_CTRL_IE_WRITE_ERROR |                \
+                             CHAN_CTRL_IE_DESC_ERROR)
+
 /* bits of the channel interrupt enable mask */
 #define CHAN_IM_DESC_ERROR                     BIT(19)
 #define CHAN_IM_READ_ERROR                     BIT(9)