spi: s3c64xx: switch exynos850 to new port config data

Exynos850 has the same version of USI SPI (v2.1) as GS101.
Drop the fifo_lvl_mask and rx_lvl_offset and switch to the new port
config data.

Backward compatibility with DT is not broken because when alises are
set:
- the SPI core will set the bus number according to the alias ID
- the FIFO depth is always the same size for exynos850 (64 bytes) no
  matter the alias ID number.

Advantages of the change:
- drop dependency on the OF alias ID.
- FIFO depth is inferred from the compatible. Exynos850 integrates 3 SPI
  IPs, all with 64 bytes FIFO depths.
- use full mask for SPI_STATUS.{RX, TX}_FIFO_LVL fields. Using partial
  masks is misleading and can hide problems of the driver logic.

Just compiled tested.

Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
Link: https://msgid.link/r/20240216070555.2483977-13-tudor.ambarus@linaro.org
Tested-by: Sam Protsenko <semen.protsenko@linaro.org>
Signed-off-by: Mark Brown <broonie@kernel.org>

diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c
index 784786407d2e070b0916ec2d1cc89d1bbdcccf37..9fcbe040cb2f2e0b8f8fb916d1c867c1c1949332 100644 (file)
--- a/drivers/spi/spi-s3c64xx.c
+++ b/drivers/spi/spi-s3c64xx.c
@@ -1576,10 +1576,9 @@ static const struct s3c64xx_spi_port_config exynos5433_spi_port_config = {
 };
 
 static const struct s3c64xx_spi_port_config exynos850_spi_port_config = {
-       /* fifo_lvl_mask is deprecated. Use {rx, tx}_fifomask instead. */
-       .fifo_lvl_mask  = { 0x7f, 0x7f, 0x7f },
-       /* rx_lvl_offset is deprecated. Use {rx, tx}_fifomask instead. */
-       .rx_lvl_offset  = 15,
+       .fifo_depth     = 64,
+       .rx_fifomask    = S3C64XX_SPI_ST_RX_FIFO_RDY_V2,
+       .tx_fifomask    = S3C64XX_SPI_ST_TX_FIFO_RDY_V2,
        .tx_st_done     = 25,
        .clk_div        = 4,
        .high_speed     = true,