drm/amd/pm: correct the usage for 'supported' member of smu_feature structure
authorEvan Quan <evan.quan@amd.com>
Wed, 8 Dec 2021 04:19:17 +0000 (12:19 +0800)
committerAlex Deucher <alexander.deucher@amd.com>
Mon, 7 Feb 2022 23:01:16 +0000 (18:01 -0500)
The supported features should be retrieved just after EnableAllDpmFeatures message
complete. And the check(whether some dpm feature is supported) is only needed when we
decide to enable or disable it.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c
drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c
drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.c
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
drivers/gpu/drm/amd/pm/swsmu/smu13/yellow_carp_ppt.c

index 86cd8341de6508b0376715ea00f19063a69d670e..40e7adf8e9ac43dc163c7535cd2291f0fd64e0bb 100644 (file)
@@ -1057,8 +1057,10 @@ static int smu_get_thermal_temperature_range(struct smu_context *smu)
 
 static int smu_smc_hw_setup(struct smu_context *smu)
 {
+       struct smu_feature *feature = &smu->smu_feature;
        struct amdgpu_device *adev = smu->adev;
        uint32_t pcie_gen = 0, pcie_width = 0;
+       uint64_t features_supported;
        int ret = 0;
 
        if (adev->in_suspend && smu_is_dpm_running(smu)) {
@@ -1138,6 +1140,15 @@ static int smu_smc_hw_setup(struct smu_context *smu)
                return ret;
        }
 
+       ret = smu_feature_get_enabled_mask(smu, &features_supported);
+       if (ret) {
+               dev_err(adev->dev, "Failed to retrieve supported dpm features!\n");
+               return ret;
+       }
+       bitmap_copy(feature->supported,
+                   (unsigned long *)&features_supported,
+                   feature->feature_num);
+
        if (!smu_is_dpm_running(smu))
                dev_info(adev->dev, "dpm has been disabled\n");
 
index 84cbde3f913d0b59c4e5bf0a35eef06123657699..f55ead5f9abaeccae34a239111f5fbe0f30880e8 100644 (file)
@@ -1624,8 +1624,8 @@ static int navi10_display_config_changed(struct smu_context *smu)
        int ret = 0;
 
        if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
-           smu_cmn_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) &&
-           smu_cmn_feature_is_supported(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
+           smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) &&
+           smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
                ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays,
                                                  smu->display_config->num_display,
                                                  NULL);
@@ -1860,13 +1860,13 @@ static int navi10_notify_smc_display_config(struct smu_context *smu)
        min_clocks.dcef_clock_in_sr = smu->display_config->min_dcef_deep_sleep_set_clk;
        min_clocks.memory_clock = smu->display_config->min_mem_set_clock;
 
-       if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
+       if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
                clock_req.clock_type = amd_pp_dcef_clock;
                clock_req.clock_freq_in_khz = min_clocks.dcef_clock * 10;
 
                ret = smu_v11_0_display_clock_voltage_request(smu, &clock_req);
                if (!ret) {
-                       if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_DCEFCLK_BIT)) {
+                       if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DS_DCEFCLK_BIT)) {
                                ret = smu_cmn_send_smc_msg_with_param(smu,
                                                                  SMU_MSG_SetMinDeepSleepDcefclk,
                                                                  min_clocks.dcef_clock_in_sr/100,
index b6759f8b5167ab07cef7c69af1c42f118ce4db1a..804e1c98238d707f59bf5bbc29491359ab72c16d 100644 (file)
@@ -1280,8 +1280,8 @@ static int sienna_cichlid_display_config_changed(struct smu_context *smu)
        int ret = 0;
 
        if ((smu->watermarks_bitmap & WATERMARKS_EXIST) &&
-           smu_cmn_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) &&
-           smu_cmn_feature_is_supported(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
+           smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT) &&
+           smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT)) {
 #if 0
                ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_NumOfDisplays,
                                                  smu->display_config->num_display,
@@ -1517,13 +1517,13 @@ static int sienna_cichlid_notify_smc_display_config(struct smu_context *smu)
        min_clocks.dcef_clock_in_sr = smu->display_config->min_dcef_deep_sleep_set_clk;
        min_clocks.memory_clock = smu->display_config->min_mem_set_clock;
 
-       if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
+       if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_DCEFCLK_BIT)) {
                clock_req.clock_type = amd_pp_dcef_clock;
                clock_req.clock_freq_in_khz = min_clocks.dcef_clock * 10;
 
                ret = smu_v11_0_display_clock_voltage_request(smu, &clock_req);
                if (!ret) {
-                       if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_DCEFCLK_BIT)) {
+                       if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DS_DCEFCLK_BIT)) {
                                ret = smu_cmn_send_smc_msg_with_param(smu,
                                                                  SMU_MSG_SetMinDeepSleepDcefclk,
                                                                  min_clocks.dcef_clock_in_sr/100,
@@ -3785,7 +3785,7 @@ static int sienna_cichlid_gpo_control(struct smu_context *smu,
        int ret = 0;
 
 
-       if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DPM_GFX_GPO_BIT)) {
+       if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFX_GPO_BIT)) {
                ret = smu_cmn_get_smc_version(smu, NULL, &smu_version);
                if (ret)
                        return ret;
index b34d3a416939696c3031b3167d9d37b9d41a1b71..d36b6437149214092edcb4019439a750f0fc1b5d 100644 (file)
@@ -808,7 +808,6 @@ int smu_v11_0_system_features_control(struct smu_context *smu,
                return ret;
 
        bitmap_zero(feature->enabled, feature->feature_num);
-       bitmap_zero(feature->supported, feature->feature_num);
 
        if (en) {
                ret = smu_cmn_get_enabled_mask(smu, &feature_mask);
@@ -817,8 +816,6 @@ int smu_v11_0_system_features_control(struct smu_context *smu,
 
                bitmap_copy(feature->enabled, (unsigned long *)&feature_mask,
                            feature->feature_num);
-               bitmap_copy(feature->supported, (unsigned long *)&feature_mask,
-                           feature->feature_num);
        }
 
        return ret;
index 65f30cdafc8fd60545bc518042dcf33c17fea932..478151e72889f2394a867d74236e562c6d86b211 100644 (file)
@@ -1956,7 +1956,6 @@ static int vangogh_system_features_control(struct smu_context *smu, bool en)
                                                      RLC_STATUS_OFF, NULL);
 
        bitmap_zero(feature->enabled, feature->feature_num);
-       bitmap_zero(feature->supported, feature->feature_num);
 
        if (!en)
                return ret;
@@ -1967,8 +1966,6 @@ static int vangogh_system_features_control(struct smu_context *smu, bool en)
 
        bitmap_copy(feature->enabled, (unsigned long *)&feature_mask,
                    feature->feature_num);
-       bitmap_copy(feature->supported, (unsigned long *)&feature_mask,
-                   feature->feature_num);
 
        return 0;
 }
@@ -1985,7 +1982,7 @@ static int vangogh_post_smu_init(struct smu_context *smu)
                adev->gfx.config.max_sh_per_se * adev->gfx.config.max_shader_engines;
 
        /* allow message will be sent after enable message on Vangogh*/
-       if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DPM_GFXCLK_BIT) &&
+       if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT) &&
                        (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) {
                ret = smu_cmn_send_smc_msg(smu, SMU_MSG_EnableGfxOff, NULL);
                if (ret) {
index 6b77fc4b4698f86fff27f1047833d7416a955aad..92b5c1108a2e36f330fe3137dccaec8b22b7476b 100644 (file)
@@ -774,7 +774,6 @@ int smu_v13_0_system_features_control(struct smu_context *smu,
                return ret;
 
        bitmap_zero(feature->enabled, feature->feature_num);
-       bitmap_zero(feature->supported, feature->feature_num);
 
        if (en) {
                ret = smu_cmn_get_enabled_mask(smu, &feature_mask);
@@ -783,8 +782,6 @@ int smu_v13_0_system_features_control(struct smu_context *smu,
 
                bitmap_copy(feature->enabled, (unsigned long *)&feature_mask,
                            feature->feature_num);
-               bitmap_copy(feature->supported, (unsigned long *)&feature_mask,
-                           feature->feature_num);
        }
 
        return ret;
index a7aabb8079edb20b7a88a038701f2fac3b1104ea..d89e8a03651b9ab61670dd27c49a6bb9c26149ed 100644 (file)
@@ -204,7 +204,6 @@ static int yellow_carp_system_features_control(struct smu_context *smu, bool en)
                ret = smu_cmn_send_smc_msg(smu, SMU_MSG_PrepareMp1ForUnload, NULL);
 
        bitmap_zero(feature->enabled, feature->feature_num);
-       bitmap_zero(feature->supported, feature->feature_num);
 
        if (!en)
                return ret;
@@ -215,8 +214,6 @@ static int yellow_carp_system_features_control(struct smu_context *smu, bool en)
 
        bitmap_copy(feature->enabled, (unsigned long *)&feature_mask,
                    feature->feature_num);
-       bitmap_copy(feature->supported, (unsigned long *)&feature_mask,
-                   feature->feature_num);
 
        return 0;
 }