arm64: dts: qcom: sm8350: Fix the base addresses of LLCC banks

The LLCC block has several banks each with a different base address
and holes in between. So it is not a correct approach to cover these
banks with a single offset/size. Instead, the individual bank's base
address needs to be specified in devicetree with the exact size.

Reported-by: Parikshit Pareek <quic_ppareek@quicinc.com>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230314080443.64635-10-manivannan.sadhasivam@linaro.org

diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi
index e31043dd48a6f845b10fc9eb620dc57027e90d15..2a9248baa204704bde6d0921217d9b081c727a5d 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
@@ -2213,8 +2213,11 @@
 
                system-cache-controller@9200000 {
                        compatible = "qcom,sm8350-llcc";
-                       reg = <0 0x09200000 0 0x1d0000>, <0 0x09600000 0 0x50000>;
-                       reg-names = "llcc_base", "llcc_broadcast_base";
+                       reg = <0 0x09200000 0 0x58000>, <0 0x09280000 0 0x58000>,
+                             <0 0x09300000 0 0x58000>, <0 0x09380000 0 0x58000>,
+                             <0 0x09600000 0 0x58000>;
+                       reg-names = "llcc0_base", "llcc1_base", "llcc2_base",
+                                   "llcc3_base", "llcc_broadcast_base";
                };
 
                compute_noc: interconnect@a0c0000 {