Setting PLL profile is the same for all ASICs, except for GOYA.
However, because this function is never called from common code, there
is no need to have an asic-specific callback function.
Signed-off-by: Oded Gabbay <ogabbay@kernel.org>
                        hl_fw_static_init_cpu(hdev, fw_loader);
 }
 
-void hl_fw_set_pll_profile(struct hl_device *hdev, enum hl_pll_frequency freq)
+void hl_fw_set_pll_profile(struct hl_device *hdev)
 {
        hl_fw_set_frequency(hdev, hdev->asic_prop.clk_pll_index,
                                hdev->asic_prop.max_freq_value);
 
  *                    internal memory via DMA engine.
  * @add_device_attr: add ASIC specific device attributes.
  * @handle_eqe: handle event queue entry (IRQ) from CPU-CP.
- * @set_pll_profile: change PLL profile (manual/automatic).
  * @get_events_stat: retrieve event queue entries histogram.
  * @read_pte: read MMU page table entry from DRAM.
  * @write_pte: write MMU page table entry to DRAM.
                                struct attribute_group *dev_attr_grp);
        void (*handle_eqe)(struct hl_device *hdev,
                                struct hl_eq_entry *eq_entry);
-       void (*set_pll_profile)(struct hl_device *hdev,
-                       enum hl_pll_frequency freq);
        void* (*get_events_stat)(struct hl_device *hdev, bool aggregate,
                                u32 *size);
        u64 (*read_pte)(struct hl_device *hdev, u64 addr);
 int hl_set_power(struct hl_device *hdev, int sensor_index, u32 attr, long value);
 int hl_get_power(struct hl_device *hdev, int sensor_index, u32 attr, long *value);
 int hl_fw_get_clk_rate(struct hl_device *hdev, u32 *cur_clk, u32 *max_clk);
-void hl_fw_set_pll_profile(struct hl_device *hdev, enum hl_pll_frequency freq);
+void hl_fw_set_pll_profile(struct hl_device *hdev);
 void hl_sysfs_add_dev_clk_attr(struct hl_device *hdev, struct attribute_group *dev_attr_grp);
 
 void hw_sob_get(struct hl_hw_sob *hw_sob);
 
         */
        gaudi_mmu_prepare(hdev, 1);
 
-       hdev->asic_funcs->set_pll_profile(hdev, PLL_LAST);
+       hl_fw_set_pll_profile(hdev);
 
        return 0;
 
        .debugfs_read_dma = gaudi_debugfs_read_dma,
        .add_device_attr = hl_sysfs_add_dev_clk_attr,
        .handle_eqe = gaudi_handle_eqe,
-       .set_pll_profile = hl_fw_set_pll_profile,
        .get_events_stat = gaudi_get_events_stat,
        .read_pte = gaudi_read_pte,
        .write_pte = gaudi_write_pte,
 
 
        goya->pm_mng_profile = PM_AUTO;
 
-       hdev->asic_funcs->set_pll_profile(hdev, PLL_LOW);
+       goya_set_pll_profile(hdev, PLL_LOW);
 
        schedule_delayed_work(&goya->goya_work->work_freq,
                usecs_to_jiffies(HL_PLL_LOW_JOB_FREQ_USEC));
        .debugfs_read_dma = goya_debugfs_read_dma,
        .add_device_attr = goya_add_device_attr,
        .handle_eqe = goya_handle_eqe,
-       .set_pll_profile = goya_set_pll_profile,
        .get_events_stat = goya_get_events_stat,
        .read_pte = goya_read_pte,
        .write_pte = goya_write_pte,
 
 {
        struct goya_device *goya = hdev->asic_specific;
 
+       if (!hdev->pdev)
+               return;
+
        switch (freq) {
        case PLL_HIGH:
                hl_fw_set_frequency(hdev, HL_GOYA_MME_PLL, hdev->high_pll);