pinctrl: renesas: Protect GPIO leftovers by CONFIG_PINCTRL_SH_FUNC_GPIO
authorGeert Uytterhoeven <geert+renesas@glider.be>
Wed, 28 Oct 2020 15:16:37 +0000 (16:16 +0100)
committerGeert Uytterhoeven <geert+renesas@glider.be>
Fri, 13 Nov 2020 14:37:41 +0000 (15:37 +0100)
On SuperH and ARM SH/R-Mobile SoCs, the pin control driver handles
GPIOs, too.  To reduce code size when compiling a kernel supporting only
modern SoCs, most, but not all, of the GPIO functionality is protected
by checks for CONFIG_PINCTRL_SH_FUNC_GPIO.

Factor out the remaining parts when not needed:
  1. sh_pfc_soc_info.{in,out}put describe GPIO pins that have input
     resp. output capabilities (SuperH and SH/R-Mobile).
  2. sh_pfc_soc_info.gpio_irq{,_size} describe the mapping from GPIO
     pins to interrupt numbers (SH/R-Mobile).
  3. sh_pfc_gpio_set_direction() configures GPIO direction, called from
     the GPIO driver through pinctrl_gpio_direction_{in,out}put()
     (SH/R-Mobile).  Unfortunately this function cannot just be moved to
     drivers/pinctrl/renesas/gpio.c, as it relies on knowledge of
     sh_pfc_pinctrl, which is internal to
     drivers/pinctrl/renesas/pinctrl.c.

While code size reduction is minimal, this does help in documenting
depencies.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20201028151637.1734130-9-geert+renesas@glider.be
drivers/pinctrl/renesas/core.c
drivers/pinctrl/renesas/pinctrl.c
drivers/pinctrl/renesas/sh_pfc.h

index c528c124fb0e92592f8060ef3c0f67a8e5f7f3c3..2cc457279345b95dce9dc28d2338e3cb828e394c 100644 (file)
@@ -315,6 +315,7 @@ int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type)
                range = NULL;
                break;
 
+#ifdef CONFIG_PINCTRL_SH_PFC_GPIO
        case PINMUX_TYPE_OUTPUT:
                range = &pfc->info->output;
                break;
@@ -322,6 +323,7 @@ int sh_pfc_config_mux(struct sh_pfc *pfc, unsigned mark, int pinmux_type)
        case PINMUX_TYPE_INPUT:
                range = &pfc->info->input;
                break;
+#endif /* CONFIG_PINCTRL_SH_PFC_GPIO */
 
        default:
                return -EINVAL;
index d5c798e98c18abee64ce08abe6ca554034097c45..ac542d278a387de1a90bfc1bf1f4e291c343ce4e 100644 (file)
@@ -435,6 +435,7 @@ static void sh_pfc_gpio_disable_free(struct pinctrl_dev *pctldev,
        spin_unlock_irqrestore(&pfc->lock, flags);
 }
 
+#ifdef CONFIG_PINCTRL_SH_PFC_GPIO
 static int sh_pfc_gpio_set_direction(struct pinctrl_dev *pctldev,
                                     struct pinctrl_gpio_range *range,
                                     unsigned offset, bool input)
@@ -462,6 +463,9 @@ static int sh_pfc_gpio_set_direction(struct pinctrl_dev *pctldev,
        spin_unlock_irqrestore(&pfc->lock, flags);
        return ret;
 }
+#else
+#define sh_pfc_gpio_set_direction      NULL
+#endif
 
 static const struct pinmux_ops sh_pfc_pinmux_ops = {
        .get_functions_count    = sh_pfc_get_functions_count,
index 3b390dffacb4910d58a0abdc41f01f5ebb7909d9..dc484c13f59c74e5651dc9e42da449010c4b22fa 100644 (file)
@@ -270,8 +270,13 @@ struct sh_pfc_soc_info {
        const char *name;
        const struct sh_pfc_soc_operations *ops;
 
+#ifdef CONFIG_PINCTRL_SH_PFC_GPIO
        struct pinmux_range input;
        struct pinmux_range output;
+       const struct pinmux_irq *gpio_irq;
+       unsigned int gpio_irq_size;
+#endif
+
        struct pinmux_range function;
 
        const struct sh_pfc_pin *pins;
@@ -295,9 +300,6 @@ struct sh_pfc_soc_info {
        const u16 *pinmux_data;
        unsigned int pinmux_data_size;
 
-       const struct pinmux_irq *gpio_irq;
-       unsigned int gpio_irq_size;
-
        u32 unlock_reg;
 };