habanalabs/gaudi2: assigning PQFs for ARC f/w in PDMA

Assigning 3 PQFs in PDMA1 and 2 PQFs in PDMA0 for ARC firmware usage.

Signed-off-by: Rajarama Manjukody Bhat <rmbhat@habana.ai>
Reviewed-by: Oded Gabbay <ogabbay@kernel.org>
Signed-off-by: Oded Gabbay <ogabbay@kernel.org>

diff --git a/drivers/misc/habanalabs/gaudi2/gaudi2.c b/drivers/misc/habanalabs/gaudi2/gaudi2.c
index fa806e5b66801b192b70b73ce57bc9a40d313d93..c907e0fbf182f346c5aad2f4ed3003dc56f0bc06 100644 (file)
--- a/drivers/misc/habanalabs/gaudi2/gaudi2.c
+++ b/drivers/misc/habanalabs/gaudi2/gaudi2.c
@@ -4175,11 +4175,15 @@ static void gaudi2_init_qman_common(struct hl_device *hdev, u32 reg_base,
        WREG32(reg_base + QM_GLBL_CFG2_OFFSET, 0);
 
        /* Enable the QMAN channel.
-        * PDMA1 QMAN configuration is different, as we do not allow user to
-        * access CP2/3, it is reserved for the ARC usage.
+        * PDMA QMAN configuration is different, as we do not allow user to
+        * access some of the CPs.
+        * PDMA0: CP2/3 are reserved for the ARC usage.
+        * PDMA1: CP1/2/3 are reserved for the ARC usage.
         */
        if (reg_base == gaudi2_qm_blocks_bases[GAUDI2_QUEUE_ID_PDMA_1_0])
                WREG32(reg_base + QM_GLBL_CFG0_OFFSET, PDMA1_QMAN_ENABLE);
+       else if (reg_base == gaudi2_qm_blocks_bases[GAUDI2_QUEUE_ID_PDMA_0_0])
+               WREG32(reg_base + QM_GLBL_CFG0_OFFSET, PDMA0_QMAN_ENABLE);
        else
                WREG32(reg_base + QM_GLBL_CFG0_OFFSET, QMAN_ENABLE);
 }
@@ -5580,10 +5584,11 @@ static bool gaudi2_is_queue_enabled(struct hl_device *hdev, u32 hw_queue_id)
        u64 hw_test_cap_bit = 0;
 
        switch (hw_queue_id) {
-       case GAUDI2_QUEUE_ID_PDMA_0_0 ... GAUDI2_QUEUE_ID_PDMA_1_1:
+       case GAUDI2_QUEUE_ID_PDMA_0_0:
+       case GAUDI2_QUEUE_ID_PDMA_0_1:
+       case GAUDI2_QUEUE_ID_PDMA_1_0:
                hw_cap_mask = HW_CAP_PDMA_MASK;
                break;
-
        case GAUDI2_QUEUE_ID_DCORE0_EDMA_0_0...GAUDI2_QUEUE_ID_DCORE0_EDMA_1_3:
                hw_test_cap_bit = HW_CAP_EDMA_SHIFT +
                        ((hw_queue_id - GAUDI2_QUEUE_ID_DCORE0_EDMA_0_0) >> 2);

diff --git a/drivers/misc/habanalabs/gaudi2/gaudi2_masks.h b/drivers/misc/habanalabs/gaudi2/gaudi2_masks.h
index eed16d642a5a43b051abcdcec4abd4fad6ee569b..0239d118abc51cc4ec36ebd529a4cfbe1d49e28c 100644 (file)
--- a/drivers/misc/habanalabs/gaudi2/gaudi2_masks.h
+++ b/drivers/misc/habanalabs/gaudi2/gaudi2_masks.h
@@ -51,12 +51,18 @@
        (0x1F << PDMA0_QM_GLBL_CFG0_CP_EN_SHIFT)  | \
        (0x1 << PDMA0_QM_GLBL_CFG0_ARC_CQF_EN_SHIFT))
 
-#define PDMA1_QMAN_ENABLE      \
+#define PDMA0_QMAN_ENABLE      \
        ((0x3 << PDMA0_QM_GLBL_CFG0_PQF_EN_SHIFT) | \
        (0x1F << PDMA0_QM_GLBL_CFG0_CQF_EN_SHIFT) | \
        (0x1F << PDMA0_QM_GLBL_CFG0_CP_EN_SHIFT)  | \
        (0x1 << PDMA0_QM_GLBL_CFG0_ARC_CQF_EN_SHIFT))
 
+#define PDMA1_QMAN_ENABLE      \
+       ((0x1 << PDMA0_QM_GLBL_CFG0_PQF_EN_SHIFT) | \
+       (0x1F << PDMA0_QM_GLBL_CFG0_CQF_EN_SHIFT) | \
+       (0x1F << PDMA0_QM_GLBL_CFG0_CP_EN_SHIFT)  | \
+       (0x1 << PDMA0_QM_GLBL_CFG0_ARC_CQF_EN_SHIFT))
+
 /* QM_IDLE_MASK is valid for all engines QM idle check */
 #define QM_IDLE_MASK   (DCORE0_EDMA0_QM_GLBL_STS0_PQF_IDLE_MASK | \
                        DCORE0_EDMA0_QM_GLBL_STS0_CQF_IDLE_MASK | \