phy: qcom-qmp: pcs: Add v7 register offsets

The X1E80100 platform bumps the HW version of QMP phy to v7 for USB,
and PCIe. Add the new PCS offsets in a dedicated header file.

Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20231122-phy-qualcomm-v6-v6-20-v7-new-offsets-v3-3-dfd1c375ef61@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>

diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v7.h b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v7.h
new file mode 100644 (file)
index 0000000..c775989
--- /dev/null
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcs-v7.h
@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2023, Linaro Limited
+ */
+
+#ifndef QCOM_PHY_QMP_PCS_V7_H_
+#define QCOM_PHY_QMP_PCS_V7_H_
+
+/* Only for QMP V7 PHY - USB/PCIe PCS registers */
+#define QPHY_V7_PCS_SW_RESET                   0x000
+#define QPHY_V7_PCS_PCS_STATUS1                        0x014
+#define QPHY_V7_PCS_POWER_DOWN_CONTROL         0x040
+#define QPHY_V7_PCS_START_CONTROL              0x044
+#define QPHY_V7_PCS_POWER_STATE_CONFIG1                0x090
+#define QPHY_V7_PCS_LOCK_DETECT_CONFIG1                0x0c4
+#define QPHY_V7_PCS_LOCK_DETECT_CONFIG2                0x0c8
+#define QPHY_V7_PCS_LOCK_DETECT_CONFIG3                0x0cc
+#define QPHY_V7_PCS_LOCK_DETECT_CONFIG6                0x0d8
+#define QPHY_V7_PCS_REFGEN_REQ_CONFIG1         0x0dc
+#define QPHY_V7_PCS_RX_SIGDET_LVL              0x188
+#define QPHY_V7_PCS_RCVR_DTCT_DLY_P1U2_L       0x190
+#define QPHY_V7_PCS_RCVR_DTCT_DLY_P1U2_H       0x194
+#define QPHY_V7_PCS_RATE_SLEW_CNTRL1           0x198
+#define QPHY_V7_PCS_CDR_RESET_TIME             0x1b0
+#define QPHY_V7_PCS_ALIGN_DETECT_CONFIG1       0x1c0
+#define QPHY_V7_PCS_ALIGN_DETECT_CONFIG2       0x1c4
+#define QPHY_V7_PCS_PCS_TX_RX_CONFIG           0x1d0
+#define QPHY_V7_PCS_EQ_CONFIG1                 0x1dc
+#define QPHY_V7_PCS_EQ_CONFIG2                 0x1e0
+#define QPHY_V7_PCS_EQ_CONFIG5                 0x1ec
+
+#endif

diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.h b/drivers/phy/qualcomm/phy-qcom-qmp.h
index 71f063f4a56e3d6234792af5332fd4104a6e9e25..21f6a56e7ae3710cda321c6d558b56052661e3a2 100644 (file)
--- a/drivers/phy/qualcomm/phy-qcom-qmp.h
+++ b/drivers/phy/qualcomm/phy-qcom-qmp.h
@@ -44,6 +44,8 @@
 
 #include "phy-qcom-qmp-pcs-v6_20.h"
 
+#include "phy-qcom-qmp-pcs-v7.h"
+
 /* Only for QMP V3 & V4 PHY - DP COM registers */
 #define QPHY_V3_DP_COM_PHY_MODE_CTRL                   0x00
 #define QPHY_V3_DP_COM_SW_RESET                                0x04