drm/amd/display: Disconnect phantom pipe OPP from OPTC being disabled

[Why]
If an OPP is used for a different OPTC without first being disconnected
from the previous OPTC, unexpected behaviour can occur. This also
applies to phantom pipes, which is what the current logic missed.

[How]
Disconnect OPPs from OPTC for phantom pipes before disabling OTG master.

Also move the disconnection to before the OTG master disable, since the
register is double buffered.

Reviewed-by: Dillon Varone <dillon.varone@amd.com>
Acked-by: Rodrigo Siqueira <rodrigo.siqueira@amd.com>
Signed-off-by: George Shen <george.shen@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c b/drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c
index 91ea0d4da06a9443bb199759fde0c75ae44fc8f3..1788eb29474b45f1221ba93cfabe5dfc0e156d0d 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c
+++ b/drivers/gpu/drm/amd/display/dc/optc/dcn32/dcn32_optc.c
@@ -166,12 +166,6 @@ static bool optc32_disable_crtc(struct timing_generator *optc)
 {
        struct optc *optc1 = DCN10TG_FROM_TG(optc);
 
-       /* disable otg request until end of the first line
-        * in the vertical blank region
-        */
-       REG_UPDATE(OTG_CONTROL,
-                       OTG_MASTER_EN, 0);
-
        REG_UPDATE_5(OPTC_DATA_SOURCE_SELECT,
                        OPTC_SEG0_SRC_SEL, 0xf,
                        OPTC_SEG1_SRC_SEL, 0xf,
@@ -179,6 +173,12 @@ static bool optc32_disable_crtc(struct timing_generator *optc)
                        OPTC_SEG3_SRC_SEL, 0xf,
                        OPTC_NUM_OF_INPUT_SEGMENT, 0);
 
+       /* disable otg request until end of the first line
+        * in the vertical blank region
+        */
+       REG_UPDATE(OTG_CONTROL,
+                       OTG_MASTER_EN, 0);
+
        REG_UPDATE(CONTROL,
                        VTG0_ENABLE, 0);
 
@@ -205,6 +205,13 @@ static void optc32_disable_phantom_otg(struct timing_generator *optc)
 {
        struct optc *optc1 = DCN10TG_FROM_TG(optc);
 
+       REG_UPDATE_5(OPTC_DATA_SOURCE_SELECT,
+                       OPTC_SEG0_SRC_SEL, 0xf,
+                       OPTC_SEG1_SRC_SEL, 0xf,
+                       OPTC_SEG2_SRC_SEL, 0xf,
+                       OPTC_SEG3_SRC_SEL, 0xf,
+                       OPTC_NUM_OF_INPUT_SEGMENT, 0);
+
        REG_UPDATE(OTG_CONTROL, OTG_MASTER_EN, 0);
 }
 

diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c b/drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c
index 08a59cf449cae5c27fe7dbe8fc1b2f847f462f9f..3d6c1b2c2b4d6e6a4ea2e28f0342c140cb045fa4 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c
+++ b/drivers/gpu/drm/amd/display/dc/optc/dcn35/dcn35_optc.c
@@ -138,12 +138,6 @@ static bool optc35_disable_crtc(struct timing_generator *optc)
 {
        struct optc *optc1 = DCN10TG_FROM_TG(optc);
 
-       /* disable otg request until end of the first line
-        * in the vertical blank region
-        */
-       REG_UPDATE(OTG_CONTROL,
-                       OTG_MASTER_EN, 0);
-
        REG_UPDATE_5(OPTC_DATA_SOURCE_SELECT,
                        OPTC_SEG0_SRC_SEL, 0xf,
                        OPTC_SEG1_SRC_SEL, 0xf,
@@ -151,6 +145,12 @@ static bool optc35_disable_crtc(struct timing_generator *optc)
                        OPTC_SEG3_SRC_SEL, 0xf,
                        OPTC_NUM_OF_INPUT_SEGMENT, 0);
 
+       /* disable otg request until end of the first line
+        * in the vertical blank region
+        */
+       REG_UPDATE(OTG_CONTROL,
+                       OTG_MASTER_EN, 0);
+
        REG_UPDATE(CONTROL,
                        VTG0_ENABLE, 0);