IMX_PINCTRL_PIN(MX25_PAD_BOOT_MODE1),
 };
 
-static struct imx_pinctrl_soc_info imx25_pinctrl_info = {
+static const struct imx_pinctrl_soc_info imx25_pinctrl_info = {
        .pins = imx25_pinctrl_pads,
        .npins = ARRAY_SIZE(imx25_pinctrl_pads),
 };
 
        IMX_PINCTRL_PIN(MX35_PAD_TEST_MODE),
 };
 
-static struct imx_pinctrl_soc_info imx35_pinctrl_info = {
+static const struct imx_pinctrl_soc_info imx35_pinctrl_info = {
        .pins = imx35_pinctrl_pads,
        .npins = ARRAY_SIZE(imx35_pinctrl_pads),
 };
 
        IMX_PINCTRL_PIN(MX50_PAD_EIM_CRE),
 };
 
-static struct imx_pinctrl_soc_info imx50_pinctrl_info = {
+static const struct imx_pinctrl_soc_info imx50_pinctrl_info = {
        .pins = imx50_pinctrl_pads,
        .npins = ARRAY_SIZE(imx50_pinctrl_pads),
        .gpr_compatible = "fsl,imx50-iomuxc-gpr",
 
        IMX_PINCTRL_PIN(MX51_PAD_CSI1_MCLK),
 };
 
-static struct imx_pinctrl_soc_info imx51_pinctrl_info = {
+static const struct imx_pinctrl_soc_info imx51_pinctrl_info = {
        .pins = imx51_pinctrl_pads,
        .npins = ARRAY_SIZE(imx51_pinctrl_pads),
 };
 
        IMX_PINCTRL_PIN(MX53_PAD_GPIO_18),
 };
 
-static struct imx_pinctrl_soc_info imx53_pinctrl_info = {
+static const struct imx_pinctrl_soc_info imx53_pinctrl_info = {
        .pins = imx53_pinctrl_pads,
        .npins = ARRAY_SIZE(imx53_pinctrl_pads),
        .gpr_compatible = "fsl,imx53-iomuxc-gpr",
 
        IMX_PINCTRL_PIN(MX6DL_PAD_SD4_DAT7),
 };
 
-static struct imx_pinctrl_soc_info imx6dl_pinctrl_info = {
+static const struct imx_pinctrl_soc_info imx6dl_pinctrl_info = {
        .pins = imx6dl_pinctrl_pads,
        .npins = ARRAY_SIZE(imx6dl_pinctrl_pads),
        .gpr_compatible = "fsl,imx6q-iomuxc-gpr",
 
        IMX_PINCTRL_PIN(MX6Q_PAD_SD2_DAT3),
 };
 
-static struct imx_pinctrl_soc_info imx6q_pinctrl_info = {
+static const struct imx_pinctrl_soc_info imx6q_pinctrl_info = {
        .pins = imx6q_pinctrl_pads,
        .npins = ARRAY_SIZE(imx6q_pinctrl_pads),
        .gpr_compatible = "fsl,imx6q-iomuxc-gpr",
 
        IMX_PINCTRL_PIN(MX6SL_PAD_WDOG_B),
 };
 
-static struct imx_pinctrl_soc_info imx6sl_pinctrl_info = {
+static const struct imx_pinctrl_soc_info imx6sl_pinctrl_info = {
        .pins = imx6sl_pinctrl_pads,
        .npins = ARRAY_SIZE(imx6sl_pinctrl_pads),
        .gpr_compatible = "fsl,imx6sl-iomuxc-gpr",
 
        IMX_PINCTRL_PIN(MX6SX_PAD_USB_H_STROBE),
 };
 
-static struct imx_pinctrl_soc_info imx6sx_pinctrl_info = {
+static const struct imx_pinctrl_soc_info imx6sx_pinctrl_info = {
        .pins = imx6sx_pinctrl_pads,
        .npins = ARRAY_SIZE(imx6sx_pinctrl_pads),
        .gpr_compatible = "fsl,imx6sx-iomuxc-gpr",
 
        return 0;
 }
 
-static struct imx_pinctrl_soc_info imx7ulp_pinctrl_info = {
+static const struct imx_pinctrl_soc_info imx7ulp_pinctrl_info = {
        .pins = imx7ulp_pinctrl_pads,
        .npins = ARRAY_SIZE(imx7ulp_pinctrl_pads),
        .flags = ZERO_OFFSET_VALID | SHARE_MUX_CONF_REG,
 
        return 0;
 }
 
-static struct imx_pinctrl_soc_info vf610_pinctrl_info = {
+static const struct imx_pinctrl_soc_info vf610_pinctrl_info = {
        .pins = vf610_pinctrl_pads,
        .npins = ARRAY_SIZE(vf610_pinctrl_pads),
        .flags = SHARE_MUX_CONF_REG | ZERO_OFFSET_VALID,