ACPICA: CXL 2.0: CEDT: Add new CEDT table
authorBen Widawsky <ben@bwidawsk.net>
Tue, 6 Apr 2021 21:30:20 +0000 (14:30 -0700)
committerRafael J. Wysocki <rafael.j.wysocki@intel.com>
Wed, 7 Apr 2021 17:09:01 +0000 (19:09 +0200)
ACPICA commit 0b03aa8ebd7a5b2b9407893f123ee587af45926f

This sets up all of the boilerplate without actually doing anything.

Link: https://github.com/acpica/acpica/commit/0b03aa8e
Signed-off-by: Ben Widawsky <ben.widawsky@intel.com>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Bob Moore <robert.moore@intel.com>
Signed-off-by: Erik Kaneda <erik.kaneda@intel.com>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
include/acpi/actbl1.h

index 2ee7eeea783be9af3e2d8da1364b4c02010df97f..7b286766e810cb40b3b77a5f74d0c527fa5de1b2 100644 (file)
@@ -28,6 +28,7 @@
 #define ACPI_SIG_BERT           "BERT" /* Boot Error Record Table */
 #define ACPI_SIG_BGRT           "BGRT" /* Boot Graphics Resource Table */
 #define ACPI_SIG_BOOT           "BOOT" /* Simple Boot Flag Table */
+#define ACPI_SIG_CEDT           "CEDT" /* CXL Early Discovery Table */
 #define ACPI_SIG_CPEP           "CPEP" /* Corrected Platform Error Polling table */
 #define ACPI_SIG_CSRT           "CSRT" /* Core System Resource Table */
 #define ACPI_SIG_DBG2           "DBG2" /* Debug Port table type 2 */
@@ -301,6 +302,48 @@ struct acpi_table_boot {
        u8 reserved[3];
 };
 
+/*******************************************************************************
+ *
+ * CEDT - CXL Early Discovery Table
+ *        Version 1
+ *
+ * Conforms to the "CXL Early Discovery Table" (CXL 2.0)
+ *
+ ******************************************************************************/
+
+struct acpi_table_cedt {
+       struct acpi_table_header header;        /* Common ACPI table header */
+};
+
+/* CEDT subtable header (Performance Record Structure) */
+
+struct acpi_cedt_header {
+       u8 type;
+       u8 reserved;
+       u16 length;
+};
+
+/* Values for Type field above */
+
+enum acpi_cedt_type {
+       ACPI_CEDT_TYPE_CHBS = 0,
+};
+
+/*
+ * CEDT subtables
+ */
+
+/* 0: CXL Host Bridge Structure */
+
+struct acpi_cedt_chbs {
+       ACPI_CEDT_HEADER header;
+       u32 uid;
+       u32 cxl_version;
+       u32 reserved;
+       u64 base;
+       u64 length;
+};
+
 /*******************************************************************************
  *
  * CPEP - Corrected Platform Error Polling table (ACPI 4.0)