clk: qcom: lpass: Add support for resets & external mclk for SC7280

The clock gating control for TX/RX/WSA core bus clocks would be required
to be reset(moved from hardware control) from audio core driver. Thus
add the support for the reset clocks.

Update the lpass_aon_cc_main_rcg_clk_src ops to park the RCG at XO after
disable as this clock signal is used by hardware to turn ON memories in
LPASS. Also add the external mclk to interface external MI2S.

Fixes: a9dd26639d05 ("clk: qcom: lpass: Add support for LPASS clock controller for SC7280")
Signed-off-by: Taniya Das <quic_tdas@quicinc.com>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/1662005846-4838-6-git-send-email-quic_c_skakit@quicinc.com

diff --git a/drivers/clk/qcom/lpassaudiocc-sc7280.c b/drivers/clk/qcom/lpassaudiocc-sc7280.c
index 606732879feae668a9397b242f37eaa1dad6c3d7..5d4bc563073cc11dce220740251d44465fc0ac3c 100644 (file)
--- a/drivers/clk/qcom/lpassaudiocc-sc7280.c
+++ b/drivers/clk/qcom/lpassaudiocc-sc7280.c
@@ -23,6 +23,7 @@
 #include "clk-regmap-mux.h"
 #include "common.h"
 #include "gdsc.h"
+#include "reset.h"
 
 enum {
        P_BI_TCXO,
@@ -248,7 +249,7 @@ static struct clk_rcg2 lpass_aon_cc_main_rcg_clk_src = {
                .parent_data = lpass_aon_cc_parent_data_0,
                .num_parents = ARRAY_SIZE(lpass_aon_cc_parent_data_0),
                .flags = CLK_OPS_PARENT_ENABLE,
-               .ops = &clk_rcg2_ops,
+               .ops = &clk_rcg2_shared_ops,
        },
 };
 
@@ -703,6 +704,18 @@ static const struct qcom_cc_desc lpass_audio_cc_sc7280_desc = {
        .num_clks = ARRAY_SIZE(lpass_audio_cc_sc7280_clocks),
 };
 
+static const struct qcom_reset_map lpass_audio_cc_sc7280_resets[] = {
+       [LPASS_AUDIO_SWR_RX_CGCR] =  { 0xa0, 1 },
+       [LPASS_AUDIO_SWR_TX_CGCR] =  { 0xa8, 1 },
+       [LPASS_AUDIO_SWR_WSA_CGCR] = { 0xb0, 1 },
+};
+
+static const struct qcom_cc_desc lpass_audio_cc_reset_sc7280_desc = {
+       .config = &lpass_audio_cc_sc7280_regmap_config,
+       .resets = lpass_audio_cc_sc7280_resets,
+       .num_resets = ARRAY_SIZE(lpass_audio_cc_sc7280_resets),
+};
+
 static const struct of_device_id lpass_audio_cc_sc7280_match_table[] = {
        { .compatible = "qcom,sc7280-lpassaudiocc" },
        { }
@@ -772,13 +785,20 @@ static int lpass_audio_cc_sc7280_probe(struct platform_device *pdev)
        regmap_write(regmap, 0x4, 0x3b);
        regmap_write(regmap, 0x8, 0xff05);
 
-       ret = qcom_cc_really_probe(pdev, &lpass_audio_cc_sc7280_desc, regmap);
+       ret = qcom_cc_probe_by_index(pdev, 0, &lpass_audio_cc_sc7280_desc);
        if (ret) {
                dev_err(&pdev->dev, "Failed to register LPASS AUDIO CC clocks\n");
                pm_runtime_disable(&pdev->dev);
                return ret;
        }
 
+       ret = qcom_cc_probe_by_index(pdev, 1, &lpass_audio_cc_reset_sc7280_desc);
+       if (ret) {
+               dev_err(&pdev->dev, "Failed to register LPASS AUDIO CC Resets\n");
+               pm_runtime_disable(&pdev->dev);
+               return ret;
+       }
+
        pm_runtime_mark_last_busy(&pdev->dev);
        pm_runtime_put_autosuspend(&pdev->dev);
        pm_runtime_put_sync(&pdev->dev);

diff --git a/drivers/clk/qcom/lpasscorecc-sc7280.c b/drivers/clk/qcom/lpasscorecc-sc7280.c
index 1f1f1bd1b68ef3a96c8c7c0eac5716a78384e6fa..6ad19b06b1ce3cd9d056b7d3ad9c1e60e67cad05 100644 (file)
--- a/drivers/clk/qcom/lpasscorecc-sc7280.c
+++ b/drivers/clk/qcom/lpasscorecc-sc7280.c
@@ -190,6 +190,19 @@ static struct clk_rcg2 lpass_core_cc_ext_if1_clk_src = {
        },
 };
 
+static struct clk_rcg2 lpass_core_cc_ext_mclk0_clk_src = {
+       .cmd_rcgr = 0x20000,
+       .mnd_width = 8,
+       .hid_width = 5,
+       .parent_map = lpass_core_cc_parent_map_0,
+       .freq_tbl = ftbl_lpass_core_cc_ext_if0_clk_src,
+       .clkr.hw.init = &(const struct clk_init_data){
+               .name = "lpass_core_cc_ext_mclk0_clk_src",
+               .parent_data = lpass_core_cc_parent_data_0,
+               .num_parents = ARRAY_SIZE(lpass_core_cc_parent_data_0),
+               .ops = &clk_rcg2_ops,
+       },
+};
 
 static struct clk_branch lpass_core_cc_core_clk = {
        .halt_reg = 0x1f000,
@@ -283,6 +296,24 @@ static struct clk_branch lpass_core_cc_lpm_mem0_core_clk = {
        },
 };
 
+static struct clk_branch lpass_core_cc_ext_mclk0_clk = {
+       .halt_reg = 0x20014,
+       .halt_check = BRANCH_HALT,
+       .clkr = {
+               .enable_reg = 0x20014,
+               .enable_mask = BIT(0),
+               .hw.init = &(const struct clk_init_data){
+                       .name = "lpass_core_cc_ext_mclk0_clk",
+                       .parent_hws = (const struct clk_hw*[]){
+                               &lpass_core_cc_ext_mclk0_clk_src.clkr.hw,
+                       },
+                       .num_parents = 1,
+                       .flags = CLK_SET_RATE_PARENT,
+                       .ops = &clk_branch2_ops,
+               },
+       },
+};
+
 static struct clk_branch lpass_core_cc_sysnoc_mport_core_clk = {
        .halt_reg = 0x23000,
        .halt_check = BRANCH_HALT_VOTED,
@@ -326,6 +357,8 @@ static struct clk_regmap *lpass_core_cc_sc7280_clocks[] = {
        [LPASS_CORE_CC_LPM_CORE_CLK] = &lpass_core_cc_lpm_core_clk.clkr,
        [LPASS_CORE_CC_LPM_MEM0_CORE_CLK] = &lpass_core_cc_lpm_mem0_core_clk.clkr,
        [LPASS_CORE_CC_SYSNOC_MPORT_CORE_CLK] = &lpass_core_cc_sysnoc_mport_core_clk.clkr,
+       [LPASS_CORE_CC_EXT_MCLK0_CLK] = &lpass_core_cc_ext_mclk0_clk.clkr,
+       [LPASS_CORE_CC_EXT_MCLK0_CLK_SRC] = &lpass_core_cc_ext_mclk0_clk_src.clkr,
 };
 
 static struct regmap_config lpass_core_cc_sc7280_regmap_config = {