memory_region_set_enabled(&fl->mmio, !!seg.size);
memory_region_transaction_commit();
+ if (asc->segment_addr_mask) {
+ regval &= asc->segment_addr_mask;
+ }
+
s->regs[R_SEG_ADDR0 + cs] = regval;
}
asc->conf_enable_w0 = CONF_ENABLE_W0;
asc->max_peripherals = 5;
asc->segments = aspeed_2400_fmc_segments;
+ asc->segment_addr_mask = 0xffff0000;
asc->resets = aspeed_2400_fmc_resets;
asc->flash_window_base = 0x20000000;
asc->flash_window_size = 0x10000000;
asc->conf_enable_w0 = CONF_ENABLE_W0;
asc->max_peripherals = 3;
asc->segments = aspeed_2500_fmc_segments;
+ asc->segment_addr_mask = 0xffff0000;
asc->resets = aspeed_2500_fmc_resets;
asc->flash_window_base = 0x20000000;
asc->flash_window_size = 0x10000000;
asc->conf_enable_w0 = CONF_ENABLE_W0;
asc->max_peripherals = 2;
asc->segments = aspeed_2500_spi1_segments;
+ asc->segment_addr_mask = 0xffff0000;
asc->flash_window_base = 0x30000000;
asc->flash_window_size = 0x8000000;
asc->features = 0x0;
asc->conf_enable_w0 = CONF_ENABLE_W0;
asc->max_peripherals = 2;
asc->segments = aspeed_2500_spi2_segments;
+ asc->segment_addr_mask = 0xffff0000;
asc->flash_window_base = 0x38000000;
asc->flash_window_size = 0x8000000;
asc->features = 0x0;
asc->conf_enable_w0 = CONF_ENABLE_W0;
asc->max_peripherals = 3;
asc->segments = aspeed_2600_fmc_segments;
+ asc->segment_addr_mask = 0x0ff00ff0;
asc->resets = aspeed_2600_fmc_resets;
asc->flash_window_base = 0x20000000;
asc->flash_window_size = 0x10000000;
asc->conf_enable_w0 = CONF_ENABLE_W0;
asc->max_peripherals = 2;
asc->segments = aspeed_2600_spi1_segments;
+ asc->segment_addr_mask = 0x0ff00ff0;
asc->flash_window_base = 0x30000000;
asc->flash_window_size = 0x10000000;
asc->features = ASPEED_SMC_FEATURE_DMA |
asc->conf_enable_w0 = CONF_ENABLE_W0;
asc->max_peripherals = 3;
asc->segments = aspeed_2600_spi2_segments;
+ asc->segment_addr_mask = 0x0ff00ff0;
asc->flash_window_base = 0x50000000;
asc->flash_window_size = 0x10000000;
asc->features = ASPEED_SMC_FEATURE_DMA |