0x1c, 0x25, 0x00, 0x40 /* 0x4000251c = UART TXD */
};
+static const uint8_t kernel_stm32vldiscovery[] = {
+ 0x00, 0x00, 0x00, 0x00, /* Stack top address */
+ 0x1d, 0x00, 0x00, 0x00, /* Reset handler address */
+ 0x00, 0x00, 0x00, 0x00, /* NMI */
+ 0x00, 0x00, 0x00, 0x00, /* Hard fault */
+ 0x00, 0x00, 0x00, 0x00, /* Memory management fault */
+ 0x00, 0x00, 0x00, 0x00, /* Bus fault */
+ 0x00, 0x00, 0x00, 0x00, /* Usage fault */
+ 0x0b, 0x4b, /* ldr r3, [pc, #44] Get RCC */
+ 0x44, 0xf2, 0x04, 0x02, /* movw r2, #16388 */
+ 0x1a, 0x60, /* str r2, [r3] */
+ 0x0a, 0x4b, /* ldr r3, [pc, #40] Get GPIOA */
+ 0x1a, 0x68, /* ldr r2, [r3] */
+ 0x22, 0xf0, 0xf0, 0x02, /* bic r2, r2, #240 */
+ 0x1a, 0x60, /* str r2, [r3] */
+ 0x1a, 0x68, /* ldr r2, [r3] */
+ 0x42, 0xf0, 0xb0, 0x02, /* orr r2, r2, #176 */
+ 0x1a, 0x60, /* str r2, [r3] */
+ 0x07, 0x4b, /* ldr r3, [pc, #26] Get BAUD */
+ 0x45, 0x22, /* movs r2, #69 */
+ 0x1a, 0x60, /* str r2, [r3] */
+ 0x06, 0x4b, /* ldr r3, [pc, #24] Get ENABLE */
+ 0x42, 0xf2, 0x08, 0x02, /* movw r2, #8200 */
+ 0x1a, 0x60, /* str r2, [r3] */
+ 0x05, 0x4b, /* ldr r3, [pc, #20] Get TXD */
+ 0x54, 0x22, /* movs r2, 'T' */
+ 0x1a, 0x60, /* str r2, [r3] */
+ 0xfe, 0xe7, /* b . */
+ 0x18, 0x10, 0x02, 0x40, /* 0x40021018 = RCC */
+ 0x04, 0x08, 0x01, 0x40, /* 0x40010804 = GPIOA */
+ 0x08, 0x38, 0x01, 0x40, /* 0x40013808 = USART1 BAUD */
+ 0x0c, 0x38, 0x01, 0x40, /* 0x4001380c = USART1 ENABLE */
+ 0x04, 0x38, 0x01, 0x40 /* 0x40013804 = USART1 TXD */
+};
+
typedef struct testdef {
const char *arch; /* Target architecture */
const char *machine; /* Name of the machine */
{ "aarch64", "virt", "-cpu max", "TT", sizeof(kernel_aarch64),
kernel_aarch64 },
{ "arm", "microbit", "", "T", sizeof(kernel_nrf51), kernel_nrf51 },
+ { "arm", "stm32vldiscovery", "", "T",
+ sizeof(kernel_stm32vldiscovery), kernel_stm32vldiscovery },
{ NULL }
};