iio: dac: ad5761: Fix alignment for DMA safety

____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1.  Switch to the updated
IIO_DMA_MINALIGN definition.

Update the comment to include 'may'.

Fixes: 131497acd88a ("iio: add ad5761 DAC driver")
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Acked-by: Nuno Sá <nuno.sa@analog.com>
Link: https://lore.kernel.org/r/20220508175712.647246-52-jic23@kernel.org

diff --git a/drivers/iio/dac/ad5761.c b/drivers/iio/dac/ad5761.c
index 4cb8471db81e07a183b8d78bd28099ea8eebafae..6aa1a068adb06172278d1e8d8a030ab20289461e 100644 (file)
--- a/drivers/iio/dac/ad5761.c
+++ b/drivers/iio/dac/ad5761.c
@@ -70,13 +70,13 @@ struct ad5761_state {
        enum ad5761_voltage_range range;
 
        /*
-        * DMA (thus cache coherency maintenance) requires the
+        * DMA (thus cache coherency maintenance) may require the
         * transfer buffers to live in their own cache lines.
         */
        union {
                __be32 d32;
                u8 d8[4];
-       } data[3] ____cacheline_aligned;
+       } data[3] __aligned(IIO_DMA_MINALIGN);
 };
 
 static const struct ad5761_range_params ad5761_range_params[] = {