spin_unlock(&priv->lock);
        if (netif_msg_tx_err(priv) && net_ratelimit())
                printk(KERN_WARNING "%s: transmit timeout\n", dev->name);
-       /* 
+       /*
         * FIXME: waking up random queue is not the best thing to
         * do... on the other hand why we got here at all?
         */
 
 
        if (!is_valid_ether_addr(ndev->dev_addr)) {
                /* try reading from mac */
-               
+
                mac_src = "chip";
                for (i = 0; i < 6; i++)
                        ndev->dev_addr[i] = ior(db, i+DM9000_PAR);
                dev_warn(db->dev, "WARNING: no IRQ resource flags set.\n");
                irqflags = DEFAULT_TRIGGER;
        }
-       
+
        irqflags |= IRQF_SHARED;
 
        if (request_irq(dev->irq, &dm9000_interrupt, irqflags, dev->name, dev))
        /* The DM9000 data sheets say we should be able to
         * poll the ERRE bit in EPCR to wait for the EEPROM
         * operation. From testing several chips, this bit
-        * does not seem to work. 
+        * does not seem to work.
         *
         * We attempt to use the bit, but fall back to the
         * timeout (which is why we do not return an error
 
 tx_irq_fail:
        free_irq(priv->interruptError, dev);
 err_irq_fail:
-err_rxalloc_fail:      
+err_rxalloc_fail:
 rx_skb_fail:
        free_skb_resources(priv);
 tx_skb_fail:
 
 NATSEMI_ATTR(dspcfg_workaround);
 
 static ssize_t natsemi_show_dspcfg_workaround(struct device *dev,
-                                             struct device_attribute *attr, 
+                                             struct device_attribute *attr,
                                              char *buf)
 {
        struct netdev_private *np = netdev_priv(to_net_dev(dev));
                  || !strncmp("0", buf, count - 1))
                new_setting = 0;
        else
-                 return count; 
+                 return count;
 
        spin_lock_irqsave(&np->lock, flags);
 
 
 #define XMAC_ADDR1                     0x000a8UL
 #define  XMAC_ADDR1_ADDR1              0x000000000000ffffULL
 
-#define XMAC_ADDR2                     0x000b0UL 
+#define XMAC_ADDR2                     0x000b0UL
 #define  XMAC_ADDR2_ADDR2              0x000000000000ffffULL
 
 #define XMAC_ADDR_CMPEN                        0x00208UL
 
       err_free_ring:
        pcnet32_free_ring(dev);
       err_free_consistent:
-       pci_free_consistent(lp->pci_dev, sizeof(*lp->init_block), 
+       pci_free_consistent(lp->pci_dev, sizeof(*lp->init_block),
                            lp->init_block, lp->init_dma_addr);
       err_free_netdev:
        free_netdev(dev);
                unregister_netdev(dev);
                pcnet32_free_ring(dev);
                release_region(dev->base_addr, PCNET32_TOTAL_SIZE);
-               pci_free_consistent(lp->pci_dev, sizeof(*lp->init_block), 
+               pci_free_consistent(lp->pci_dev, sizeof(*lp->init_block),
                                    lp->init_block, lp->init_dma_addr);
                free_netdev(dev);
                pci_disable_device(pdev);
                unregister_netdev(pcnet32_dev);
                pcnet32_free_ring(pcnet32_dev);
                release_region(pcnet32_dev->base_addr, PCNET32_TOTAL_SIZE);
-               pci_free_consistent(lp->pci_dev, sizeof(*lp->init_block), 
+               pci_free_consistent(lp->pci_dev, sizeof(*lp->init_block),
                                    lp->init_block, lp->init_dma_addr);
                free_netdev(pcnet32_dev);
                pcnet32_dev = next_dev;
 
        reg &= ~PHY_GIG_ALL_PARAMS;
 
        if(portConfiguration & PORT_CONFIG_1000MB_SPEED) {
-               if(portConfiguration & PORT_CONFIG_FULL_DUPLEX_ENABLED) 
+               if(portConfiguration & PORT_CONFIG_FULL_DUPLEX_ENABLED)
                        reg |= PHY_GIG_ADV_1000F;
-               else 
+               else
                        reg |= PHY_GIG_ADV_1000H;
        }
 
 
                if (block_no)
                        rxd_index += (block_no * ring->rxd_count);
 
-               if ((block_no == block_no1) && 
+               if ((block_no == block_no1) &&
                        (off == ring->rx_curr_get_info.offset) &&
                        (rxdp->Host_Control)) {
                        DBG_PRINT(INTR_DBG, "%s: Get and Put",
                                first_rxdp->Control_1 |= RXD_OWN_XENA;
                        }
                        stats->mem_alloc_fail_cnt++;
-                               
+
                        return -ENOMEM ;
                }
                stats->mem_allocated += skb->truesize;
 
 
        /* interface MTU value */
         unsigned mtu;
-    
+
        /* Buffer Address store. */
        struct buffAdd **ba;
 
 
        ((M_MAC_INT_EOP_COUNT | M_MAC_INT_EOP_TIMER) << S_MAC_RX_CH0),
        sc->sbm_imr);
 #else
-       __raw_writeq((M_MAC_INT_CHANNEL << S_MAC_TX_CH0) | 
+       __raw_writeq((M_MAC_INT_CHANNEL << S_MAC_TX_CH0) |
        (M_MAC_INT_CHANNEL << S_MAC_RX_CH0), sc->sbm_imr);
 #endif
 }
 
        SIS_PCI_COMMIT();
 }
 
-static int __devinit sis190_get_mac_addr(struct pci_dev *pdev, 
+static int __devinit sis190_get_mac_addr(struct pci_dev *pdev,
                                         struct net_device *dev)
 {
        int rc;
 
                                skb = sis_priv->rx_skbuff[entry];
                                net_dev->stats.rx_dropped++;
                                goto refill_rx_ring;
-                       }       
+                       }
 
                        /* This situation should never happen, but due to
                           some unknow bugs, it is possible that
 
 
                gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
        } else
-               gm_phy_write(hw, port, PHY_MARV_LED_OVER, 
+               gm_phy_write(hw, port, PHY_MARV_LED_OVER,
                                     PHY_M_LED_MO_DUP(mode) |
                                     PHY_M_LED_MO_10(mode) |
                                     PHY_M_LED_MO_100(mode) |
 
  *
  * spider_net_enable_interrupt enables several interrupts
  */
-static void 
+static void
 spider_net_enable_interrupts(struct spider_net_card *card)
 {
        spider_net_write_reg(card, SPIDER_NET_GHIINT0MSK,
  *
  * spider_net_disable_interrupts disables all the interrupts
  */
-static void 
+static void
 spider_net_disable_interrupts(struct spider_net_card *card)
 {
        spider_net_write_reg(card, SPIDER_NET_GHIINT0MSK, 0);
 
        struct tsi108_prv_data *data = netdev_priv(dev);
        unsigned long flags;
        int rc;
-       
+
        spin_lock_irqsave(&data->txlock, flags);
        rc = mii_ethtool_gset(&data->mii_if, cmd);
        spin_unlock_irqrestore(&data->txlock, flags);
        spin_lock_irqsave(&data->txlock, flags);
        rc = mii_ethtool_sset(&data->mii_if, cmd);
        spin_unlock_irqrestore(&data->txlock, flags);
-       
+
        return rc;
 }
 
 
  *
  * Author: Li Yang <leoli@freescale.com>
  *
- * Limitation: 
+ * Limitation:
  * Can only get/set setttings of the first queue.
  * Need to re-open the interface manually after changing some paramters.
  *
 
        ugeth->ug_info->receiveFlowControl = pause->rx_pause;
        ugeth->ug_info->transmitFlowControl = pause->tx_pause;
-       
+
        if (ugeth->phydev->autoneg) {
                if (netif_running(netdev)) {
                        /* FIXME: automatically restart */