drm/amd/display: FEC check in timing validation

[Why]
disable/enable leads FEC mismatch between hw/sw FEC state.

[How]
check FEC status to fastboot on/off.

Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
Acked-by: Alex Hung <alex.hung@amd.com>
Signed-off-by: Chiawen Huang <chiawen.huang@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c
index f6e19efea7568de940803065da576aab11b85fc9..75f9c97bebb00210f761403e0223622683969737 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/core/dc.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc.c
@@ -1496,6 +1496,10 @@ bool dc_validate_boot_timing(const struct dc *dc,
        if (!link->link_enc->funcs->is_dig_enabled(link->link_enc))
                return false;
 
+       /* Check for FEC status*/
+       if (link->link_enc->funcs->fec_is_active(link->link_enc))
+               return false;
+
        enc_inst = link->link_enc->funcs->get_dig_frontend(link->link_enc);
 
        if (enc_inst == ENGINE_ID_UNKNOWN)