drm/xe: Fix ROW_CHICKEN2 define

When this register was added in xe for some workarounds, it was copied
from i915 before the registers got changed to add the MCR annotation.
The register 0xe4f4 is MCR since gen8, long before any GPU supported by
the xe driver. Replace all occurrences with the right register.

Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://lore.kernel.org/r/20230306165757.633796-1-lucas.demarchi@intel.com
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
index 6a728d2809c527c97fec7565c9e7e29f31a18349..d3b862e4cd0db3a98aaffe53aaba590a85bd6893 100644 (file)
--- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
@@ -230,7 +230,7 @@
 #define   THREAD_EX_ARB_MODE                   REG_GENMASK(3, 2)
 #define   THREAD_EX_ARB_MODE_RR_AFTER_DEP      REG_FIELD_PREP(THREAD_EX_ARB_MODE, 0x2)
 
-#define GEN7_ROW_CHICKEN2                      _MMIO(0xe4f4)
+#define GEN8_ROW_CHICKEN2                      MCR_REG(0xe4f4)
 #define   GEN12_DISABLE_READ_SUPPRESSION       REG_BIT(15)
 #define   GEN12_DISABLE_EARLY_READ             REG_BIT(14)
 #define   GEN12_ENABLE_LARGE_GRF_MODE          REG_BIT(12)

diff --git a/drivers/gpu/drm/xe/xe_wa.c b/drivers/gpu/drm/xe/xe_wa.c
index 71e9e1a111f8917be9f8f3f341388901a804d5c5..03c5b01a14e40c831894d488793b388f402d337c 100644 (file)
--- a/drivers/gpu/drm/xe/xe_wa.c
+++ b/drivers/gpu/drm/xe/xe_wa.c
@@ -191,7 +191,7 @@ static const struct xe_rtp_entry engine_was[] = {
        },
        { XE_RTP_NAME("1606931601"),
          XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210), ENGINE_CLASS(RENDER)),
-         XE_RTP_ACTIONS(SET(GEN7_ROW_CHICKEN2, GEN12_DISABLE_EARLY_READ,
+         XE_RTP_ACTIONS(SET(GEN8_ROW_CHICKEN2, GEN12_DISABLE_EARLY_READ,
                             XE_RTP_ACTION_FLAG(MASKED_REG)))
        },
        { XE_RTP_NAME("22010931296, 18011464164, 14010919138"),
@@ -213,7 +213,7 @@ static const struct xe_rtp_entry engine_was[] = {
          XE_RTP_RULES(GRAPHICS_VERSION(1200),
                       ENGINE_CLASS(RENDER),
                       IS_INTEGRATED),
-         XE_RTP_ACTIONS(SET(GEN7_ROW_CHICKEN2, GEN12_PUSH_CONST_DEREF_HOLD_DIS,
+         XE_RTP_ACTIONS(SET(GEN8_ROW_CHICKEN2, GEN12_PUSH_CONST_DEREF_HOLD_DIS,
                             XE_RTP_ACTION_FLAG(MASKED_REG)))
        },
        { XE_RTP_NAME("14010229206, 1409085225"),