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Merge "ACPICA: Add CXL 3.0 structures..." into for-6.2/cxl-xor
authorDan Williams <dan.j.williams@intel.com>
Sat, 3 Dec 2022 22:43:29 +0000 (14:43 -0800)
committerDan Williams <dan.j.williams@intel.com>
Sat, 3 Dec 2022 22:43:29 +0000 (14:43 -0800)
Pick up:

f350c68e3cd5 ("ACPICA: Add CXL 3.0 structures (CXIMS & RDPAS) to the CEDT table")

...to build the new XOR interleave math support for the CXL Fixed Memory
Window Structures.


Trivial merge
ep93xx device tree rework repo: git://git.maquefel.me/linux.git