arm64: disable EL2 traps for PIE

Disable trapping of TCR2_EL1 and PIRx_EL1 registers, so they can be
accessed from by EL1.

Signed-off-by: Joey Gouly <joey.gouly@arm.com>
Cc: Will Deacon <will@kernel.org>
Reviewed-by: Mark Brown <broonie@kernel.org>
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Link: https://lore.kernel.org/r/20230606145859.697944-15-joey.gouly@arm.com
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

diff --git a/arch/arm64/include/asm/el2_setup.h b/arch/arm64/include/asm/el2_setup.h
index 0201577863ca462b9eeab4fa31f336616c1c8b93..e12a7c29aedcd6bbc98b2a7038e3279725e1a028 100644 (file)
--- a/arch/arm64/include/asm/el2_setup.h
+++ b/arch/arm64/include/asm/el2_setup.h
@@ -159,12 +159,21 @@
        mov     x0, xzr
        mrs     x1, id_aa64pfr1_el1
        ubfx    x1, x1, #ID_AA64PFR1_EL1_SME_SHIFT, #4
-       cbz     x1, .Lset_fgt_\@
+       cbz     x1, .Lset_pie_fgt_\@
 
        /* Disable nVHE traps of TPIDR2 and SMPRI */
        orr     x0, x0, #HFGxTR_EL2_nSMPRI_EL1_MASK
        orr     x0, x0, #HFGxTR_EL2_nTPIDR2_EL0_MASK
 
+.Lset_pie_fgt_\@:
+       mrs_s   x1, SYS_ID_AA64MMFR3_EL1
+       ubfx    x1, x1, #ID_AA64MMFR3_EL1_S1PIE_SHIFT, #4
+       cbz     x1, .Lset_fgt_\@
+
+       /* Disable trapping of PIR_EL1 / PIRE0_EL1 */
+       orr     x0, x0, #HFGxTR_EL2_nPIR_EL1
+       orr     x0, x0, #HFGxTR_EL2_nPIRE0_EL1
+
 .Lset_fgt_\@:
        msr_s   SYS_HFGRTR_EL2, x0
        msr_s   SYS_HFGWTR_EL2, x0

diff --git a/arch/arm64/include/asm/kvm_arm.h b/arch/arm64/include/asm/kvm_arm.h
index d2d4f4cd12b8b63713ed807fc991ea07f31debd0..c6e12e8f2751c223f3de1f6c723546bc692d1247 100644 (file)
--- a/arch/arm64/include/asm/kvm_arm.h
+++ b/arch/arm64/include/asm/kvm_arm.h
@@ -93,8 +93,8 @@
 #define HCR_HOST_NVHE_PROTECTED_FLAGS (HCR_HOST_NVHE_FLAGS | HCR_TSC)
 #define HCR_HOST_VHE_FLAGS (HCR_RW | HCR_TGE | HCR_E2H)
 
-#define HCRX_GUEST_FLAGS (HCRX_EL2_SMPME)
-#define HCRX_HOST_FLAGS (HCRX_EL2_MSCEn)
+#define HCRX_GUEST_FLAGS (HCRX_EL2_SMPME | HCRX_EL2_TCR2En)
+#define HCRX_HOST_FLAGS (HCRX_EL2_MSCEn | HCRX_EL2_TCR2En)
 
 /* TCR_EL2 Registers bits */
 #define TCR_EL2_RES1           ((1U << 31) | (1 << 23))