drm/i915: split out PCI config space registers from i915_reg.h

The PCI config space registers don't really belong next to the MMIO
register definitions.

v2: Fix	copyright year (Matt)

Cc: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220110095740.166078-1-jani.nikula@intel.com

diff --git a/drivers/gpu/drm/i915/display/intel_backlight.c b/drivers/gpu/drm/i915/display/intel_backlight.c
index 2db3b792aca6358f9e69330a59a4e605ac96bdee..98f7ea44042f264d151be819f0a201818ea33f0e 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_backlight.c
+++ b/drivers/gpu/drm/i915/display/intel_backlight.c
@@ -13,6 +13,7 @@
 #include "intel_dp_aux_backlight.h"
 #include "intel_dsi_dcs_backlight.h"
 #include "intel_panel.h"
+#include "intel_pci_config.h"
 
 /**
  * scale - scale values from one range to another

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 249f81a80eb7e4d0101fc83cd82e08557b19d10b..1f13398e8ac2746d47832f7d8c46623fdbce329f 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -31,6 +31,7 @@
 #include "intel_crtc.h"
 #include "intel_de.h"
 #include "intel_display_types.h"
+#include "intel_pci_config.h"
 #include "intel_pcode.h"
 #include "intel_psr.h"
 #include "vlv_sideband.h"

diff --git a/drivers/gpu/drm/i915/display/intel_opregion.c b/drivers/gpu/drm/i915/display/intel_opregion.c
index 985790a66a4dc91c1145d62748329fc5f4da4d8a..af9d30f56cc1a5e8905f175f1837f69b67ef138e 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_opregion.c
+++ b/drivers/gpu/drm/i915/display/intel_opregion.c
@@ -35,6 +35,7 @@
 #include "intel_backlight.h"
 #include "intel_display_types.h"
 #include "intel_opregion.h"
+#include "intel_pci_config.h"
 
 #define OPREGION_HEADER_OFFSET 0
 #define OPREGION_ACPI_OFFSET   0x100

diff --git a/drivers/gpu/drm/i915/display/intel_overlay.c b/drivers/gpu/drm/i915/display/intel_overlay.c
index 7e3f5c6ca4846f38f8a06691aead25bb8154ba77..23f30fdb35193d06fe48618aefbcd3466ff0e5f4 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_overlay.c
+++ b/drivers/gpu/drm/i915/display/intel_overlay.c
@@ -38,6 +38,7 @@
 #include "intel_display_types.h"
 #include "intel_frontbuffer.h"
 #include "intel_overlay.h"
+#include "intel_pci_config.h"
 
 /* Limits for overlay size. According to intel doc, the real limits are:
  * Y width: 4095, UV width (planar): 2047, Y height: 2047,

diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c b/drivers/gpu/drm/i915/gt/intel_reset.c
index d8fe35f2281df5da378602c342175caab8466cdc..c5bfcbe568907d8d9fb3eba46af5ecd0dad0dfe6 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_reset.c
+++ b/drivers/gpu/drm/i915/gt/intel_reset.c
@@ -19,6 +19,7 @@
 #include "intel_gt.h"
 #include "intel_gt_pm.h"
 #include "intel_gt_requests.h"
+#include "intel_pci_config.h"
 #include "intel_reset.h"
 
 #include "uc/intel_guc.h"

diff --git a/drivers/gpu/drm/i915/i915_driver.c b/drivers/gpu/drm/i915/i915_driver.c
index f7e674e229a1b664f8724a6824ac7a315be4fbd7..6a7aac069b186cde50b98503a1d71f2e9cbb63e2 100644 (file)
--- a/drivers/gpu/drm/i915/i915_driver.c
+++ b/drivers/gpu/drm/i915/i915_driver.c
@@ -87,6 +87,7 @@
 #include "intel_dram.h"
 #include "intel_gvt.h"
 #include "intel_memory_region.h"
+#include "intel_pci_config.h"
 #include "intel_pcode.h"
 #include "intel_pm.h"
 #include "intel_region_ttm.h"

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 5b502c8f0cfb67cc88ce183f3a269104ec91ba00..da310fde3fb3d06e099f8fc6381ad39c2572a53b 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -275,84 +275,6 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg)
 #define _MASKED_BIT_ENABLE(a)  ({ typeof(a) _a = (a); _MASKED_FIELD(_a, _a); })
 #define _MASKED_BIT_DISABLE(a) (_MASKED_FIELD((a), 0))
 
-/* PCI config space */
-
-#define MCHBAR_I915 0x44
-#define MCHBAR_I965 0x48
-#define MCHBAR_SIZE (4 * 4096)
-
-#define DEVEN 0x54
-#define   DEVEN_MCHBAR_EN (1 << 28)
-
-/* BSM in include/drm/i915_drm.h */
-
-#define HPLLCC 0xc0 /* 85x only */
-#define   GC_CLOCK_CONTROL_MASK                (0x7 << 0)
-#define   GC_CLOCK_133_200             (0 << 0)
-#define   GC_CLOCK_100_200             (1 << 0)
-#define   GC_CLOCK_100_133             (2 << 0)
-#define   GC_CLOCK_133_266             (3 << 0)
-#define   GC_CLOCK_133_200_2           (4 << 0)
-#define   GC_CLOCK_133_266_2           (5 << 0)
-#define   GC_CLOCK_166_266             (6 << 0)
-#define   GC_CLOCK_166_250             (7 << 0)
-
-#define I915_GDRST 0xc0 /* PCI config register */
-#define   GRDOM_FULL           (0 << 2)
-#define   GRDOM_RENDER         (1 << 2)
-#define   GRDOM_MEDIA          (3 << 2)
-#define   GRDOM_MASK           (3 << 2)
-#define   GRDOM_RESET_STATUS   (1 << 1)
-#define   GRDOM_RESET_ENABLE   (1 << 0)
-
-/* BSpec only has register offset, PCI device and bit found empirically */
-#define I830_CLOCK_GATE        0xc8 /* device 0 */
-#define   I830_L2_CACHE_CLOCK_GATE_DISABLE     (1 << 2)
-
-#define GCDGMBUS 0xcc
-
-#define GCFGC2 0xda
-#define GCFGC  0xf0 /* 915+ only */
-#define   GC_LOW_FREQUENCY_ENABLE      (1 << 7)
-#define   GC_DISPLAY_CLOCK_190_200_MHZ (0 << 4)
-#define   GC_DISPLAY_CLOCK_333_320_MHZ (4 << 4)
-#define   GC_DISPLAY_CLOCK_267_MHZ_PNV (0 << 4)
-#define   GC_DISPLAY_CLOCK_333_MHZ_PNV (1 << 4)
-#define   GC_DISPLAY_CLOCK_444_MHZ_PNV (2 << 4)
-#define   GC_DISPLAY_CLOCK_200_MHZ_PNV (5 << 4)
-#define   GC_DISPLAY_CLOCK_133_MHZ_PNV (6 << 4)
-#define   GC_DISPLAY_CLOCK_167_MHZ_PNV (7 << 4)
-#define   GC_DISPLAY_CLOCK_MASK                (7 << 4)
-#define   GM45_GC_RENDER_CLOCK_MASK    (0xf << 0)
-#define   GM45_GC_RENDER_CLOCK_266_MHZ (8 << 0)
-#define   GM45_GC_RENDER_CLOCK_320_MHZ (9 << 0)
-#define   GM45_GC_RENDER_CLOCK_400_MHZ (0xb << 0)
-#define   GM45_GC_RENDER_CLOCK_533_MHZ (0xc << 0)
-#define   I965_GC_RENDER_CLOCK_MASK    (0xf << 0)
-#define   I965_GC_RENDER_CLOCK_267_MHZ (2 << 0)
-#define   I965_GC_RENDER_CLOCK_333_MHZ (3 << 0)
-#define   I965_GC_RENDER_CLOCK_444_MHZ (4 << 0)
-#define   I965_GC_RENDER_CLOCK_533_MHZ (5 << 0)
-#define   I945_GC_RENDER_CLOCK_MASK    (7 << 0)
-#define   I945_GC_RENDER_CLOCK_166_MHZ (0 << 0)
-#define   I945_GC_RENDER_CLOCK_200_MHZ (1 << 0)
-#define   I945_GC_RENDER_CLOCK_250_MHZ (3 << 0)
-#define   I945_GC_RENDER_CLOCK_400_MHZ (5 << 0)
-#define   I915_GC_RENDER_CLOCK_MASK    (7 << 0)
-#define   I915_GC_RENDER_CLOCK_166_MHZ (0 << 0)
-#define   I915_GC_RENDER_CLOCK_200_MHZ (1 << 0)
-#define   I915_GC_RENDER_CLOCK_333_MHZ (4 << 0)
-
-#define ASLE   0xe4
-#define ASLS   0xfc
-
-#define SWSCI  0xe8
-#define   SWSCI_SCISEL (1 << 15)
-#define   SWSCI_GSSCIE (1 << 0)
-
-#define LBPC 0xf4 /* legacy/combination backlight modes, also called LBB */
-
-
 #define ILK_GDSR _MMIO(MCHBAR_MIRROR_BASE + 0x2ca4)
 #define  ILK_GRDOM_FULL                (0 << 1)
 #define  ILK_GRDOM_RENDER      (1 << 1)

diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c
index f7b55f34dba8225a25fb8db36f51c7f87c1c2807..889f5b7dc78edd6edea8856057206d3ac9c0b8f5 100644 (file)
--- a/drivers/gpu/drm/i915/i915_suspend.c
+++ b/drivers/gpu/drm/i915/i915_suspend.c
@@ -32,6 +32,7 @@
 #include "i915_drv.h"
 #include "i915_reg.h"
 #include "i915_suspend.h"
+#include "intel_pci_config.h"
 
 static void intel_save_swf(struct drm_i915_private *dev_priv)
 {

diff --git a/drivers/gpu/drm/i915/intel_pci_config.h b/drivers/gpu/drm/i915/intel_pci_config.h
new file mode 100644 (file)
index 0000000..12cd9d4
--- /dev/null
+++ b/drivers/gpu/drm/i915/intel_pci_config.h
@@ -0,0 +1,85 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2022 Intel Corporation
+ */
+
+#ifndef __INTEL_PCI_CONFIG_H__
+#define __INTEL_PCI_CONFIG_H__
+
+/* BSM in include/drm/i915_drm.h */
+
+#define MCHBAR_I915                            0x44
+#define MCHBAR_I965                            0x48
+#define   MCHBAR_SIZE                          (4 * 4096)
+
+#define DEVEN                                  0x54
+#define   DEVEN_MCHBAR_EN                      (1 << 28)
+
+#define HPLLCC                                 0xc0 /* 85x only */
+#define   GC_CLOCK_CONTROL_MASK                        (0x7 << 0)
+#define   GC_CLOCK_133_200                     (0 << 0)
+#define   GC_CLOCK_100_200                     (1 << 0)
+#define   GC_CLOCK_100_133                     (2 << 0)
+#define   GC_CLOCK_133_266                     (3 << 0)
+#define   GC_CLOCK_133_200_2                   (4 << 0)
+#define   GC_CLOCK_133_266_2                   (5 << 0)
+#define   GC_CLOCK_166_266                     (6 << 0)
+#define   GC_CLOCK_166_250                     (7 << 0)
+
+#define I915_GDRST                             0xc0
+#define   GRDOM_FULL                           (0 << 2)
+#define   GRDOM_RENDER                         (1 << 2)
+#define   GRDOM_MEDIA                          (3 << 2)
+#define   GRDOM_MASK                           (3 << 2)
+#define   GRDOM_RESET_STATUS                   (1 << 1)
+#define   GRDOM_RESET_ENABLE                   (1 << 0)
+
+/* BSpec only has register offset, PCI device and bit found empirically */
+#define I830_CLOCK_GATE                                0xc8 /* device 0 */
+#define   I830_L2_CACHE_CLOCK_GATE_DISABLE     (1 << 2)
+
+#define GCDGMBUS                               0xcc
+
+#define GCFGC2                                 0xda
+#define GCFGC                                  0xf0 /* 915+ only */
+#define   GC_LOW_FREQUENCY_ENABLE              (1 << 7)
+#define   GC_DISPLAY_CLOCK_190_200_MHZ         (0 << 4)
+#define   GC_DISPLAY_CLOCK_333_320_MHZ         (4 << 4)
+#define   GC_DISPLAY_CLOCK_267_MHZ_PNV         (0 << 4)
+#define   GC_DISPLAY_CLOCK_333_MHZ_PNV         (1 << 4)
+#define   GC_DISPLAY_CLOCK_444_MHZ_PNV         (2 << 4)
+#define   GC_DISPLAY_CLOCK_200_MHZ_PNV         (5 << 4)
+#define   GC_DISPLAY_CLOCK_133_MHZ_PNV         (6 << 4)
+#define   GC_DISPLAY_CLOCK_167_MHZ_PNV         (7 << 4)
+#define   GC_DISPLAY_CLOCK_MASK                        (7 << 4)
+#define   GM45_GC_RENDER_CLOCK_MASK            (0xf << 0)
+#define   GM45_GC_RENDER_CLOCK_266_MHZ         (8 << 0)
+#define   GM45_GC_RENDER_CLOCK_320_MHZ         (9 << 0)
+#define   GM45_GC_RENDER_CLOCK_400_MHZ         (0xb << 0)
+#define   GM45_GC_RENDER_CLOCK_533_MHZ         (0xc << 0)
+#define   I965_GC_RENDER_CLOCK_MASK            (0xf << 0)
+#define   I965_GC_RENDER_CLOCK_267_MHZ         (2 << 0)
+#define   I965_GC_RENDER_CLOCK_333_MHZ         (3 << 0)
+#define   I965_GC_RENDER_CLOCK_444_MHZ         (4 << 0)
+#define   I965_GC_RENDER_CLOCK_533_MHZ         (5 << 0)
+#define   I945_GC_RENDER_CLOCK_MASK            (7 << 0)
+#define   I945_GC_RENDER_CLOCK_166_MHZ         (0 << 0)
+#define   I945_GC_RENDER_CLOCK_200_MHZ         (1 << 0)
+#define   I945_GC_RENDER_CLOCK_250_MHZ         (3 << 0)
+#define   I945_GC_RENDER_CLOCK_400_MHZ         (5 << 0)
+#define   I915_GC_RENDER_CLOCK_MASK            (7 << 0)
+#define   I915_GC_RENDER_CLOCK_166_MHZ         (0 << 0)
+#define   I915_GC_RENDER_CLOCK_200_MHZ         (1 << 0)
+#define   I915_GC_RENDER_CLOCK_333_MHZ         (4 << 0)
+
+#define ASLE                                   0xe4
+#define ASLS                                   0xfc
+
+#define SWSCI                                  0xe8
+#define   SWSCI_SCISEL                         (1 << 15)
+#define   SWSCI_GSSCIE                         (1 << 0)
+
+/* legacy/combination backlight modes, also called LBB */
+#define LBPC                                   0xf4
+
+#endif /* __INTEL_PCI_CONFIG_H__ */