pinctrl: renesas: r8a779a0: Add HSCIF pins, groups and functions

This patch adds HSCIF0-3 pins, groups and functions to the R8A779A0
(V3U) SoC.

Signed-off-by: Ulrich Hecht <uli+renesas@fpond.eu>
Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/20210112165929.31002-6-uli+renesas@fpond.eu
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>

diff --git a/drivers/pinctrl/renesas/pfc-r8a779a0.c b/drivers/pinctrl/renesas/pfc-r8a779a0.c
index 0b5036d3f82aa188bf38d45123a140f006fc7f5b..44797b4599983ce8e28734be8e2118970da86e9b 100644 (file)
--- a/drivers/pinctrl/renesas/pfc-r8a779a0.c
+++ b/drivers/pinctrl/renesas/pfc-r8a779a0.c
@@ -1810,6 +1810,98 @@ static const unsigned int du_oddf_mux[] = {
        DU_ODDF_DISP_CDE_MARK,
 };
 
+/* - HSCIF0 ----------------------------------------------------------------- */
+static const unsigned int hscif0_data_pins[] = {
+       /* HRX0, HTX0 */
+       RCAR_GP_PIN(1, 1), RCAR_GP_PIN(1, 5),
+};
+static const unsigned int hscif0_data_mux[] = {
+       HRX0_MARK, HTX0_MARK,
+};
+static const unsigned int hscif0_clk_pins[] = {
+       /* HSCK0 */
+       RCAR_GP_PIN(1, 2),
+};
+static const unsigned int hscif0_clk_mux[] = {
+       HSCK0_MARK,
+};
+static const unsigned int hscif0_ctrl_pins[] = {
+       /* HRTS0#, HCTS0# */
+       RCAR_GP_PIN(1, 3), RCAR_GP_PIN(1, 4),
+};
+static const unsigned int hscif0_ctrl_mux[] = {
+       HRTS0_N_MARK, HCTS0_N_MARK,
+};
+
+/* - HSCIF1 ----------------------------------------------------------------- */
+static const unsigned int hscif1_data_pins[] = {
+       /* HRX1, HTX1 */
+       RCAR_GP_PIN(1, 21), RCAR_GP_PIN(1, 22),
+};
+static const unsigned int hscif1_data_mux[] = {
+       HRX1_MARK, HTX1_MARK,
+};
+static const unsigned int hscif1_clk_pins[] = {
+       /* HSCK1 */
+       RCAR_GP_PIN(1, 18),
+};
+static const unsigned int hscif1_clk_mux[] = {
+       HSCK1_MARK,
+};
+static const unsigned int hscif1_ctrl_pins[] = {
+       /* HRTS1#, HCTS1# */
+       RCAR_GP_PIN(1, 20), RCAR_GP_PIN(1, 19),
+};
+static const unsigned int hscif1_ctrl_mux[] = {
+       HRTS1_N_MARK, HCTS1_N_MARK,
+};
+
+/* - HSCIF2 ----------------------------------------------------------------- */
+static const unsigned int hscif2_data_pins[] = {
+       /* HRX2, HTX2 */
+       RCAR_GP_PIN(2, 8), RCAR_GP_PIN(2, 9),
+};
+static const unsigned int hscif2_data_mux[] = {
+       HRX2_MARK, HTX2_MARK,
+};
+static const unsigned int hscif2_clk_pins[] = {
+       /* HSCK2 */
+       RCAR_GP_PIN(2, 5),
+};
+static const unsigned int hscif2_clk_mux[] = {
+       HSCK2_MARK,
+};
+static const unsigned int hscif2_ctrl_pins[] = {
+       /* HRTS2#, HCTS2# */
+       RCAR_GP_PIN(2, 7), RCAR_GP_PIN(2, 6),
+};
+static const unsigned int hscif2_ctrl_mux[] = {
+       HRTS2_N_MARK, HCTS2_N_MARK,
+};
+
+/* - HSCIF3 ----------------------------------------------------------------- */
+static const unsigned int hscif3_data_pins[] = {
+       /* HRX3, HTX3 */
+       RCAR_GP_PIN(1, 13), RCAR_GP_PIN(1, 17),
+};
+static const unsigned int hscif3_data_mux[] = {
+       HRX3_MARK, HTX3_MARK,
+};
+static const unsigned int hscif3_clk_pins[] = {
+       /* HSCK3 */
+       RCAR_GP_PIN(1, 14),
+};
+static const unsigned int hscif3_clk_mux[] = {
+       HSCK3_MARK,
+};
+static const unsigned int hscif3_ctrl_pins[] = {
+       /* HRTS3#, HCTS3# */
+       RCAR_GP_PIN(1, 15), RCAR_GP_PIN(1, 16),
+};
+static const unsigned int hscif3_ctrl_mux[] = {
+       HRTS3_N_MARK, HCTS3_N_MARK,
+};
+
 /* - I2C0 ------------------------------------------------------------------- */
 static const unsigned int i2c0_pins[] = {
        /* SDA0, SCL0 */
@@ -2057,6 +2149,19 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
        SH_PFC_PIN_GROUP(du_sync),
        SH_PFC_PIN_GROUP(du_oddf),
 
+       SH_PFC_PIN_GROUP(hscif0_data),
+       SH_PFC_PIN_GROUP(hscif0_clk),
+       SH_PFC_PIN_GROUP(hscif0_ctrl),
+       SH_PFC_PIN_GROUP(hscif1_data),
+       SH_PFC_PIN_GROUP(hscif1_clk),
+       SH_PFC_PIN_GROUP(hscif1_ctrl),
+       SH_PFC_PIN_GROUP(hscif2_data),
+       SH_PFC_PIN_GROUP(hscif2_clk),
+       SH_PFC_PIN_GROUP(hscif2_ctrl),
+       SH_PFC_PIN_GROUP(hscif3_data),
+       SH_PFC_PIN_GROUP(hscif3_clk),
+       SH_PFC_PIN_GROUP(hscif3_ctrl),
+
        SH_PFC_PIN_GROUP(i2c0),
        SH_PFC_PIN_GROUP(i2c1),
        SH_PFC_PIN_GROUP(i2c2),
@@ -2196,6 +2301,30 @@ static const char * const du_groups[] = {
        "du_oddf",
 };
 
+static const char * const hscif0_groups[] = {
+       "hscif0_data",
+       "hscif0_clk",
+       "hscif0_ctrl",
+};
+
+static const char * const hscif1_groups[] = {
+       "hscif1_data",
+       "hscif1_clk",
+       "hscif1_ctrl",
+};
+
+static const char * const hscif2_groups[] = {
+       "hscif2_data",
+       "hscif2_clk",
+       "hscif2_ctrl",
+};
+
+static const char * const hscif3_groups[] = {
+       "hscif3_data",
+       "hscif3_clk",
+       "hscif3_ctrl",
+};
+
 static const char * const i2c0_groups[] = {
        "i2c0",
 };
@@ -2273,6 +2402,11 @@ static const struct sh_pfc_function pinmux_functions[] = {
 
        SH_PFC_FUNCTION(du),
 
+       SH_PFC_FUNCTION(hscif0),
+       SH_PFC_FUNCTION(hscif1),
+       SH_PFC_FUNCTION(hscif2),
+       SH_PFC_FUNCTION(hscif3),
+
        SH_PFC_FUNCTION(i2c0),
        SH_PFC_FUNCTION(i2c1),
        SH_PFC_FUNCTION(i2c2),