drm/amd/display: Add extra logging for HUBP and OTG

[Description]
Add extra logging for DCSURF_FLIP_CNTL, DCHUBP_CNTL,
OTG_MASTER_EN, and OTG_DOUBLE_BUFFER_CONTROL for more
debuggability for a system crash.

Reviewed-by: Samson Tam <samson.tam@amd.com>
Acked-by: Roman Li <roman.li@amd.com>
Signed-off-by: Alvin Lee <alvin.lee2@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h
index 09784222cc0336ae87c5b3387f3155c2c2abee75..69119b2fdce23b878f9148e62cfa37a7820ac30f 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h
@@ -692,6 +692,7 @@ struct dcn_hubp_state {
        uint32_t primary_meta_addr_hi;
        uint32_t uclk_pstate_force;
        uint32_t hubp_cntl;
+       uint32_t flip_control;
 };
 
 struct dcn10_hubp {

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c
index 89c3bf0fe0c9916d3d725f4d4a72cce2ef349077..6bba020ad6fbfe7d8a453214a5a38ef3c449ab40 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c
@@ -1331,6 +1331,12 @@ void hubp2_read_state(struct hubp *hubp)
                SWATH_HEIGHT_C, &rq_regs->rq_regs_c.swath_height,
                PTE_ROW_HEIGHT_LINEAR_C, &rq_regs->rq_regs_c.pte_row_height_linear);
 
+       if (REG(DCHUBP_CNTL))
+               s->hubp_cntl = REG_READ(DCHUBP_CNTL);
+
+       if (REG(DCSURF_FLIP_CONTROL))
+               s->flip_control = REG_READ(DCSURF_FLIP_CONTROL);
+
 }
 
 static void hubp2_validate_dml_output(struct hubp *hubp,

diff --git a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hubp.c b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hubp.c
index 75547ce86c09bc9e41d809f4e5c5ee8b4b1214eb..60a64d290352743f2d6ad1148be45d275df89bd0 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hubp.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn30/dcn30_hubp.c
@@ -455,6 +455,9 @@ void hubp3_read_state(struct hubp *hubp)
        if (REG(DCHUBP_CNTL))
                s->hubp_cntl = REG_READ(DCHUBP_CNTL);
 
+       if (REG(DCSURF_FLIP_CONTROL))
+               s->flip_control = REG_READ(DCSURF_FLIP_CONTROL);
+
 }
 
 void hubp3_setup(

diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/optc.h b/drivers/gpu/drm/amd/display/dc/inc/hw/optc.h
index 9a8bf6ec70ea6668417abea564d6711f6b7c8afa..8d32e525f05a034e46b7269be97d729dc2f20eb5 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/optc.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/optc.h
@@ -93,6 +93,8 @@ struct dcn_otg_state {
        uint32_t vertical_interrupt1_line;
        uint32_t vertical_interrupt2_en;
        uint32_t vertical_interrupt2_line;
+       uint32_t otg_master_update_lock;
+       uint32_t otg_double_buffer_control;
 };
 
 void optc1_read_otg_state(struct optc *optc1, struct dcn_otg_state *s);

diff --git a/drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c b/drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
index 0e8f4f36c87c517dac7544afd815c32650fc12a7..f109a101d84f3499adca396816f0a4202054d24c 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
+++ b/drivers/gpu/drm/amd/display/dc/optc/dcn10/dcn10_optc.c
@@ -1383,6 +1383,9 @@ void optc1_read_otg_state(struct optc *optc1,
 
        REG_GET(OTG_VERTICAL_INTERRUPT2_POSITION,
                        OTG_VERTICAL_INTERRUPT2_LINE_START, &s->vertical_interrupt2_line);
+
+       s->otg_master_update_lock = REG_READ(OTG_MASTER_UPDATE_LOCK);
+       s->otg_double_buffer_control = REG_READ(OTG_DOUBLE_BUFFER_CONTROL);
 }
 
 bool optc1_get_otg_active_size(struct timing_generator *optc,