drm/xe/xelpmp: Extend Wa_22016670082 to Xe_LPM+
authorShekhar Chauhan <shekhar.chauhan@intel.com>
Mon, 30 Oct 2023 15:07:56 +0000 (20:37 +0530)
committerRodrigo Vivi <rodrigo.vivi@intel.com>
Thu, 21 Dec 2023 16:43:31 +0000 (11:43 -0500)
Add Xe_LPM+ support to an existing workaround.

BSpec: 51762
Signed-off-by: Shekhar Chauhan <shekhar.chauhan@intel.com>
Link: https://lore.kernel.org/r/20231030150756.1011777-1-shekhar.chauhan@intel.com
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
drivers/gpu/drm/xe/regs/xe_gt_regs.h
drivers/gpu/drm/xe/xe_wa.c

index b00fe089525a5ac63bd337531aede9421f121ac1..7a6407e38265a5a2176382cb82c9e5df8ecb17c7 100644 (file)
 #define   POLYGON_TRIFAN_LINELOOP_DISABLE      REG_BIT(4)
 
 #define SQCNT1                                 XE_REG_MCR(0x8718)
+#define XELPMP_SQCNT1                          XE_REG(0x8718)
 #define   ENFORCE_RAR                          REG_BIT(23)
 
 #define XEHP_SQCM                              XE_REG_MCR(0x8724)
index ce61609b001cbae860d1527967ffa1530fe2e3f7..2f1782db267b6c388460509c25b29e38bf4e4b29 100644 (file)
@@ -246,6 +246,13 @@ static const struct xe_rtp_entry_sr gt_was[] = {
          XE_RTP_ACTIONS(SET(SQCNT1, ENFORCE_RAR))
        },
 
+       /* Xe_LPM+ */
+
+       { XE_RTP_NAME("22016670082"),
+         XE_RTP_RULES(MEDIA_VERSION(1300)),
+         XE_RTP_ACTIONS(SET(XELPMP_SQCNT1, ENFORCE_RAR))
+       },
+
        /* Xe2_LPG */
 
        { XE_RTP_NAME("16020975621"),