wifi: rtw89: mac: generalize register of MU-EDCA switch according to chip gen

When connected with 802.11ax AP, MU-EDCA parameters are given, so enable
this hardware function by registers according to chip generation.

Signed-off-by: Zong-Zhe Yang <kevin_yang@realtek.com>
Signed-off-by: Ping-Ke Shih <pkshih@realtek.com>
Signed-off-by: Kalle Valo <kvalo@kernel.org>
Link: https://lore.kernel.org/r/20231012021455.19816-3-pkshih@realtek.com

diff --git a/drivers/net/wireless/realtek/rtw89/mac.c b/drivers/net/wireless/realtek/rtw89/mac.c
index 4587bd596c32a7c3b67402e5db1b244c05a3ef0a..d2621f31a78a8635c3787b34632bf8e9d53f92ad 100644 (file)
--- a/drivers/net/wireless/realtek/rtw89/mac.c
+++ b/drivers/net/wireless/realtek/rtw89/mac.c
@@ -5593,8 +5593,9 @@ int rtw89_mac_get_tx_retry_limit(struct rtw89_dev *rtwdev,
 int rtw89_mac_set_hw_muedca_ctrl(struct rtw89_dev *rtwdev,
                                 struct rtw89_vif *rtwvif, bool en)
 {
+       const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
        u8 mac_idx = rtwvif->mac_idx;
-       u16 set = B_AX_MUEDCA_EN_0 | B_AX_SET_MUEDCATIMER_TF_0;
+       u16 set = mac->muedca_ctrl.mask;
        u32 reg;
        u32 ret;
 
@@ -5602,7 +5603,7 @@ int rtw89_mac_set_hw_muedca_ctrl(struct rtw89_dev *rtwdev,
        if (ret)
                return ret;
 
-       reg = rtw89_mac_reg_by_idx(rtwdev, R_AX_MUEDCA_EN, mac_idx);
+       reg = rtw89_mac_reg_by_idx(rtwdev, mac->muedca_ctrl.addr, mac_idx);
        if (en)
                rtw89_write16_set(rtwdev, reg, set);
        else
@@ -5754,6 +5755,11 @@ const struct rtw89_mac_gen_def rtw89_mac_gen_ax = {
        .port_base = &rtw89_port_base_ax,
        .agg_len_ht = R_AX_AGG_LEN_HT_0,
 
+       .muedca_ctrl = {
+               .addr = R_AX_MUEDCA_EN,
+               .mask = B_AX_MUEDCA_EN_0 | B_AX_SET_MUEDCATIMER_TF_0,
+       },
+
        .disable_cpu = rtw89_mac_disable_cpu_ax,
        .fwdl_enable_wcpu = rtw89_mac_enable_cpu_ax,
        .fwdl_get_status = rtw89_fw_get_rdy_ax,

diff --git a/drivers/net/wireless/realtek/rtw89/mac.h b/drivers/net/wireless/realtek/rtw89/mac.h
index b318027a977f22dcdac067d692668dd515bfc3be..982b357ec6f1db4ecb8446dd318985062ac2f029 100644 (file)
--- a/drivers/net/wireless/realtek/rtw89/mac.h
+++ b/drivers/net/wireless/realtek/rtw89/mac.h
@@ -861,6 +861,8 @@ struct rtw89_mac_gen_def {
        const struct rtw89_port_reg *port_base;
        u32 agg_len_ht;
 
+       struct rtw89_reg_def muedca_ctrl;
+
        void (*disable_cpu)(struct rtw89_dev *rtwdev);
        int (*fwdl_enable_wcpu)(struct rtw89_dev *rtwdev, u8 boot_reason,
                                bool dlfw, bool include_bb);

diff --git a/drivers/net/wireless/realtek/rtw89/mac_be.c b/drivers/net/wireless/realtek/rtw89/mac_be.c
index 6c277b6b25b8c3c197857431264737c2159814e4..514cf566eba19d13809f41104dda62356b9fd2b9 100644 (file)
--- a/drivers/net/wireless/realtek/rtw89/mac_be.c
+++ b/drivers/net/wireless/realtek/rtw89/mac_be.c
@@ -252,6 +252,11 @@ const struct rtw89_mac_gen_def rtw89_mac_gen_be = {
        .port_base = &rtw89_port_base_be,
        .agg_len_ht = R_BE_AGG_LEN_HT_0,
 
+       .muedca_ctrl = {
+               .addr = R_BE_MUEDCA_EN,
+               .mask = B_BE_MUEDCA_EN_0 | B_BE_SET_MUEDCATIMER_TF_0,
+       },
+
        .disable_cpu = rtw89_mac_disable_cpu_be,
        .fwdl_enable_wcpu = rtw89_mac_fwdl_enable_wcpu_be,
        .fwdl_get_status = fwdl_get_status_be,

diff --git a/drivers/net/wireless/realtek/rtw89/reg.h b/drivers/net/wireless/realtek/rtw89/reg.h
index 8c148d6041d0cc514eb3333a78a7d2c358700808..96d5959c299e5e3aac0d5d8e512b6ac0d0b0ec18 100644 (file)
--- a/drivers/net/wireless/realtek/rtw89/reg.h
+++ b/drivers/net/wireless/realtek/rtw89/reg.h
@@ -3780,6 +3780,13 @@
 #define B_BE_P0_SYNC_PORT_SRC_SEL_MASK GENMASK(26, 24)
 #define B_BE_P0_TSFTR_SYNC_OFFSET_MASK GENMASK(18, 0)
 
+#define R_BE_MUEDCA_EN 0x10370
+#define R_BE_MUEDCA_EN_C1 0x14370
+#define B_BE_MUEDCA_WMM_SEL BIT(8)
+#define B_BE_SET_MUEDCATIMER_TF_1 BIT(5)
+#define B_BE_SET_MUEDCATIMER_TF_0 BIT(4)
+#define B_BE_MUEDCA_EN_0 BIT(0)
+
 #define R_BE_PORT_CFG_P0 0x10400
 #define R_BE_PORT_CFG_P0_C1 0x14400
 #define B_BE_BCN_ERLY_SORT_EN_P0 BIT(18)