arm64: dts: qcom: sm8550: Add USB PHYs and controller nodes

Add USB host controller and PHY nodes.

Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230119004533.1869870-2-abel.vesa@linaro.org

diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
index 26e6009325773e91068aec8974daf08adad07cae..6ff135191ee09d6222726e349877065a9e689688 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
@@ -14,6 +14,7 @@
 #include <dt-bindings/mailbox/qcom-ipcc.h>
 #include <dt-bindings/power/qcom-rpmpd.h>
 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
+#include <dt-bindings/phy/phy-qcom-qmp.h>
 #include <dt-bindings/thermal/thermal.h>
 
 / {
@@ -746,7 +747,7 @@
                                 <&ufs_mem_phy 0>,
                                 <&ufs_mem_phy 1>,
                                 <&ufs_mem_phy 2>,
-                                <0>;
+                                <&usb_dp_qmpphy QMP_USB43DP_USB3_PIPE_CLK>;
                };
 
                ipcc: mailbox@408000 {
@@ -2369,6 +2370,95 @@
                        status = "disabled";
                };
 
+               usb_1_hsphy: phy@88e3000 {
+                       compatible = "qcom,sm8550-snps-eusb2-phy";
+                       reg = <0x0 0x088e3000 0x0 0x154>;
+                       #phy-cells = <0>;
+
+                       clocks = <&tcsr TCSR_USB2_CLKREF_EN>;
+                       clock-names = "ref";
+
+                       resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
+
+                       status = "disabled";
+               };
+
+               usb_dp_qmpphy: phy@88e8000 {
+                       compatible = "qcom,sm8550-qmp-usb3-dp-phy";
+                       reg = <0x0 0x088e8000 0x0 0x3000>;
+
+                       clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
+                                <&rpmhcc RPMH_CXO_CLK>,
+                                <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
+                                <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
+                       clock-names = "aux", "ref", "com_aux", "usb3_pipe";
+
+                       power-domains = <&gcc USB3_PHY_GDSC>;
+
+                       resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
+                                <&gcc GCC_USB3_PHY_PRIM_BCR>;
+                       reset-names = "phy", "common";
+
+                       #clock-cells = <1>;
+                       #phy-cells = <1>;
+
+                       status = "disabled";
+               };
+
+               usb_1: usb@a6f8800 {
+                       compatible = "qcom,sm8550-dwc3", "qcom,dwc3";
+                       reg = <0x0 0x0a6f8800 0x0 0x400>;
+                       #address-cells = <2>;
+                       #size-cells = <2>;
+                       ranges;
+
+                       clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
+                                <&gcc GCC_USB30_PRIM_MASTER_CLK>,
+                                <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
+                                <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
+                                <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
+                                <&tcsr TCSR_USB3_CLKREF_EN>;
+                       clock-names = "cfg_noc",
+                                     "core",
+                                     "iface",
+                                     "sleep",
+                                     "mock_utmi",
+                                     "xo";
+
+                       assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
+                                         <&gcc GCC_USB30_PRIM_MASTER_CLK>;
+                       assigned-clock-rates = <19200000>, <200000000>;
+
+                       interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
+                                             <&pdc 17 IRQ_TYPE_LEVEL_HIGH>,
+                                             <&pdc 15 IRQ_TYPE_EDGE_RISING>,
+                                             <&pdc 14 IRQ_TYPE_EDGE_RISING>;
+                       interrupt-names = "hs_phy_irq",
+                                         "ss_phy_irq",
+                                         "dm_hs_phy_irq",
+                                         "dp_hs_phy_irq";
+
+                       power-domains = <&gcc USB30_PRIM_GDSC>;
+                       required-opps = <&rpmhpd_opp_nom>;
+
+                       resets = <&gcc GCC_USB30_PRIM_BCR>;
+
+                       status = "disabled";
+
+                       usb_1_dwc3: usb@a600000 {
+                               compatible = "snps,dwc3";
+                               reg = <0x0 0x0a600000 0x0 0xcd00>;
+                               interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
+                               iommus = <&apps_smmu 0x40 0x0>;
+                               snps,dis_u2_susphy_quirk;
+                               snps,dis_enblslpm_quirk;
+                               snps,usb3_lpm_capable;
+                               phys = <&usb_1_hsphy>,
+                                      <&usb_dp_qmpphy QMP_USB43DP_USB3_PHY>;
+                               phy-names = "usb2-phy", "usb3-phy";
+                       };
+               };
+
                pdc: interrupt-controller@b220000 {
                        compatible = "qcom,sm8550-pdc", "qcom,pdc";
                        reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>;