clk: rockchip: rk3568: Add PLL rate for 101MHz

This patch adds PLL setting for not so common resolution as 1920x720-50.00,
which can be set using 2500 horizontal signals and 808 vertical.

Signed-off-by: Alibek Omarov <a1ba.omarov@gmail.com>
Reviewed-by: Sascha Hauer <s.hauer@pengutronix.de>
Link: https://lore.kernel.org/r/20230614134716.1055862-1-a1ba.omarov@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

diff --git a/drivers/clk/rockchip/clk-rk3568.c b/drivers/clk/rockchip/clk-rk3568.c
index f85902e2590c7feaad6884dbf9d6400148676494..5dae960af4ceeeecca25d7d08bdfd2ddc1033202 100644 (file)
--- a/drivers/clk/rockchip/clk-rk3568.c
+++ b/drivers/clk/rockchip/clk-rk3568.c
@@ -79,6 +79,7 @@ static struct rockchip_pll_rate_table rk3568_pll_rates[] = {
        RK3036_PLL_RATE(135000000, 2, 45, 4, 1, 1, 0),
        RK3036_PLL_RATE(119000000, 3, 119, 4, 2, 1, 0),
        RK3036_PLL_RATE(108000000, 2, 45, 5, 1, 1, 0),
+       RK3036_PLL_RATE(101000000, 1, 101, 6, 4, 1, 0),
        RK3036_PLL_RATE(100000000, 1, 150, 6, 6, 1, 0),
        RK3036_PLL_RATE(96000000, 1, 96, 6, 4, 1, 0),
        RK3036_PLL_RATE(78750000, 1, 96, 6, 4, 1, 0),