drm/msm: De-open-code some CP_EVENT_WRITE

Replace some open coding to improve readability.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/499272/
Link: https://lore.kernel.org/r/20220821155441.1092134-1-robdclark@gmail.com

diff --git a/drivers/gpu/drm/msm/adreno/a3xx_gpu.c b/drivers/gpu/drm/msm/adreno/a3xx_gpu.c
index 0ab0e1dd8bbb0706dbbc5f524e96ae832a760656..2c8b9899625b06bba642010acef5fb0b1be37865 100644 (file)
--- a/drivers/gpu/drm/msm/adreno/a3xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a3xx_gpu.c
@@ -68,7 +68,7 @@ static void a3xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit)
 
        /* BIT(31) of CACHE_FLUSH_TS triggers CACHE_FLUSH_TS IRQ from GPU */
        OUT_PKT3(ring, CP_EVENT_WRITE, 3);
-       OUT_RING(ring, CACHE_FLUSH_TS | BIT(31));
+       OUT_RING(ring, CACHE_FLUSH_TS | CP_EVENT_WRITE_0_IRQ);
        OUT_RING(ring, rbmemptr(ring, fence));
        OUT_RING(ring, submit->seqno);
 

diff --git a/drivers/gpu/drm/msm/adreno/a4xx_gpu.c b/drivers/gpu/drm/msm/adreno/a4xx_gpu.c
index 0c6b2a6d0b4c95e9ab894fc9e99252c4f4db7cf7..7cb8d9849c07327097ce383c246f923e4190b93e 100644 (file)
--- a/drivers/gpu/drm/msm/adreno/a4xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a4xx_gpu.c
@@ -62,7 +62,7 @@ static void a4xx_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit)
 
        /* BIT(31) of CACHE_FLUSH_TS triggers CACHE_FLUSH_TS IRQ from GPU */
        OUT_PKT3(ring, CP_EVENT_WRITE, 3);
-       OUT_RING(ring, CACHE_FLUSH_TS | BIT(31));
+       OUT_RING(ring, CACHE_FLUSH_TS | CP_EVENT_WRITE_0_IRQ);
        OUT_RING(ring, rbmemptr(ring, fence));
        OUT_RING(ring, submit->seqno);
 

diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
index 4d501100b9e45e445a17a3a3418298634bd19db9..c8ad8aeca777f1d491421753303e0db3f5a6d984 100644 (file)
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
@@ -146,7 +146,7 @@ static void a6xx_set_pagetable(struct a6xx_gpu *a6xx_gpu,
         */
 
        OUT_PKT7(ring, CP_EVENT_WRITE, 1);
-       OUT_RING(ring, 0x31);
+       OUT_RING(ring, CACHE_INVALIDATE);
 
        if (!sysprof) {
                /*