target-mips: Correct the handling of register #72 on writes

Fix an off-by-one error in `mips_cpu_gdb_write_register' for register
matching how `mips_cpu_gdb_read_register' handles it.  This register
slot is a fake anyway, there's nothing in hardware that corresponds to
it.

Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com>
Reviewed-by: Leon Alrae <leon.alrae@imgtec.com>
Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>

diff --git a/target-mips/gdbstub.c b/target-mips/gdbstub.c
index f65fec23cc310bd70d7f2e71a3107c4358f9d88e..7e3a604afa5e08b4d0a9d8e9e0996281557702c0 100644 (file)
--- a/target-mips/gdbstub.c
+++ b/target-mips/gdbstub.c
@@ -90,7 +90,7 @@ int mips_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
         return sizeof(target_ulong);
     }
     if (env->CP0_Config1 & (1 << CP0C1_FP)
-            && n >= 38 && n < 73) {
+            && n >= 38 && n < 72) {
         if (n < 70) {
             if (env->CP0_Status & (1 << CP0St_FR)) {
                 env->active_fpu.fpr[n - 38].d = tmp;