MIPS: Fix Ingenic SoCs sometimes reporting wrong ISA

The config0 register in the Xburst CPUs with a processor ID of
PRID_COMP_INGENIC_D0 report themselves as MIPS32r2 compatible,
but they don't actually support this ISA.

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Paul Burton <paul.burton@mips.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: James Hogan <jhogan@kernel.org>
Cc: od@zcrc.me
Cc: linux-mips@vger.kernel.org
Cc: linux-kernel@vger.kernel.org

diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index d5e335e6846a9645a96ffb556014d16f32053d38..6126b77d5a62b0a6674e80a9d3628ada18e9d0f1 100644 (file)
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -1973,6 +1973,14 @@ static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu)
                panic("Unknown Ingenic Processor ID!");
                break;
        }
+
+       /*
+        * The config0 register in the Xburst CPUs with a processor ID of
+        * PRID_COMP_INGENIC_D0 report themselves as MIPS32r2 compatible,
+        * but they don't actually support this ISA.
+        */
+       if ((c->processor_id & PRID_COMP_MASK) == PRID_COMP_INGENIC_D0)
+               c->isa_level &= ~MIPS_CPU_ISA_M32R2;
 }
 
 static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu)