MIPS: Sanitise Cavium switch cases in TLB handler synthesizers

[ Upstream commit 6ddcba9d480b6bcced4223a729794dfa6becb7eb ]

It makes no sense to fall through to `break'.  Therefore reorder the
switch statements so as to have the Cavium cases first, followed by the
default case, which improves readability and pacifies code analysis
tools.  No change in semantics, assembly produced is exactly the same.

Reported-by: kernel test robot <lkp@intel.com>
Signed-off-by: Maciej W. Rozycki <macro@orcam.me.uk>
Fixes: bc431d2153cc ("MIPS: Fix fall-through warnings for Clang")
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Signed-off-by: Sasha Levin <sashal@kernel.org>

diff --git a/arch/mips/mm/tlbex.c b/arch/mips/mm/tlbex.c
index 9adad24c2e65e55f8ecd4bc6c24f0c8560efbd89..046d51a454afc1fe97218b328cc52977fd9e832d 100644 (file)
--- a/arch/mips/mm/tlbex.c
+++ b/arch/mips/mm/tlbex.c
@@ -2167,16 +2167,14 @@ static void build_r4000_tlb_load_handler(void)
                uasm_i_tlbr(&p);
 
                switch (current_cpu_type()) {
-               default:
-                       if (cpu_has_mips_r2_exec_hazard) {
-                               uasm_i_ehb(&p);
-                       fallthrough;
-
                case CPU_CAVIUM_OCTEON:
                case CPU_CAVIUM_OCTEON_PLUS:
                case CPU_CAVIUM_OCTEON2:
-                               break;
-                       }
+                       break;
+               default:
+                       if (cpu_has_mips_r2_exec_hazard)
+                               uasm_i_ehb(&p);
+                       break;
                }
 
                /* Examine  entrylo 0 or 1 based on ptr. */
@@ -2243,15 +2241,14 @@ static void build_r4000_tlb_load_handler(void)
                uasm_i_tlbr(&p);
 
                switch (current_cpu_type()) {
-               default:
-                       if (cpu_has_mips_r2_exec_hazard) {
-                               uasm_i_ehb(&p);
-
                case CPU_CAVIUM_OCTEON:
                case CPU_CAVIUM_OCTEON_PLUS:
                case CPU_CAVIUM_OCTEON2:
-                               break;
-                       }
+                       break;
+               default:
+                       if (cpu_has_mips_r2_exec_hazard)
+                               uasm_i_ehb(&p);
+                       break;
                }
 
                /* Examine  entrylo 0 or 1 based on ptr. */