Merge branches 'clk-versa', 'clk-silabs', 'clk-samsung', 'clk-starfive' and 'clk...

 - Add glitch free PLL setting support to si5351 clk driver

* clk-versa:
  clk: versaclock3: Drop ret variable
  clk: versaclock3: Add missing space between ')' and '{'
  clk: versaclock3: Use u8 return type for get_parent() callback
  clk: versaclock3: Avoid unnecessary padding
  clk: versaclock3: Update vc3_get_div() to avoid divide by zero

* clk-silabs:
  clk: si5351: allow PLLs to be adjusted without reset
  dt-bindings: clock: si5351: add PLL reset mode property
  dt-bindings: clock: si5351: convert to yaml

* clk-samsung:
  clk: samsung: Improve kernel-doc comments
  clk: samsung: Fix kernel-doc comments

* clk-starfive:
  clk: starfive: jh7100: Add CLK_SET_RATE_PARENT to gmac_tx
  clk: starfive: Add flags argument to JH71X0__MUX macro

* clk-sophgo:
  dt-bindings: clock: sophgo: Add clock controller of CV1800 series SoC