soc: qcom: geni: Optimize/comment select fifo/dma mode

The functions geni_se_select_fifo_mode() and
geni_se_select_fifo_mode() are a little funny.  They read/write a
bunch of memory mapped registers even if they don't change or aren't
relevant for the current protocol.  Let's make them a little more
sane.  We'll also add a comment explaining why we don't do some of the
operations for UART.

NOTE: there is no evidence at all that this makes any performance
difference and it fixes no bugs.  However, it seems (to me) like it
makes the functions a little easier to understand.  Decreasing the
amount of times we read/write memory mapped registers is also nice,
even if we are using "relaxed" variants.

Signed-off-by: Douglas Anderson <dianders@chromium.org>
Link: https://lore.kernel.org/r/20201013142448.v2.3.I646736d3969dc47de8daceb379c6ba85993de9f4@changeid
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

diff --git a/drivers/soc/qcom/qcom-geni-se.c b/drivers/soc/qcom/qcom-geni-se.c
index 751a49f6534f45f19829d88dfb86a3d896180e9e..7649b2057b9a7a7a5f9bf688e1e75d87ca2c21d7 100644 (file)
--- a/drivers/soc/qcom/qcom-geni-se.c
+++ b/drivers/soc/qcom/qcom-geni-se.c
@@ -266,49 +266,63 @@ EXPORT_SYMBOL(geni_se_init);
 static void geni_se_select_fifo_mode(struct geni_se *se)
 {
        u32 proto = geni_se_read_proto(se);
-       u32 val;
+       u32 val, val_old;
 
        geni_se_irq_clear(se);
 
-       val = readl_relaxed(se->base + SE_GENI_M_IRQ_EN);
+       /*
+        * The RX path for the UART is asynchronous and so needs more
+        * complex logic for enabling / disabling its interrupts.
+        *
+        * Specific notes:
+        * - The done and TX-related interrupts are managed manually.
+        * - We don't RX from the main sequencer (we use the secondary) so
+        *   we don't need the RX-related interrupts enabled in the main
+        *   sequencer for UART.
+        */
        if (proto != GENI_SE_UART) {
+               val_old = val = readl_relaxed(se->base + SE_GENI_M_IRQ_EN);
                val |= M_CMD_DONE_EN | M_TX_FIFO_WATERMARK_EN;
                val |= M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN;
-       }
-       writel_relaxed(val, se->base + SE_GENI_M_IRQ_EN);
+               if (val != val_old)
+                       writel_relaxed(val, se->base + SE_GENI_M_IRQ_EN);
 
-       val = readl_relaxed(se->base + SE_GENI_S_IRQ_EN);
-       if (proto != GENI_SE_UART)
+               val_old = val = readl_relaxed(se->base + SE_GENI_S_IRQ_EN);
                val |= S_CMD_DONE_EN;
-       writel_relaxed(val, se->base + SE_GENI_S_IRQ_EN);
+               if (val != val_old)
+                       writel_relaxed(val, se->base + SE_GENI_S_IRQ_EN);
+       }
 
-       val = readl_relaxed(se->base + SE_GENI_DMA_MODE_EN);
+       val_old = val = readl_relaxed(se->base + SE_GENI_DMA_MODE_EN);
        val &= ~GENI_DMA_MODE_EN;
-       writel_relaxed(val, se->base + SE_GENI_DMA_MODE_EN);
+       if (val != val_old)
+               writel_relaxed(val, se->base + SE_GENI_DMA_MODE_EN);
 }
 
 static void geni_se_select_dma_mode(struct geni_se *se)
 {
        u32 proto = geni_se_read_proto(se);
-       u32 val;
+       u32 val, val_old;
 
        geni_se_irq_clear(se);
 
-       val = readl_relaxed(se->base + SE_GENI_M_IRQ_EN);
        if (proto != GENI_SE_UART) {
+               val_old = val = readl_relaxed(se->base + SE_GENI_M_IRQ_EN);
                val &= ~(M_CMD_DONE_EN | M_TX_FIFO_WATERMARK_EN);
                val &= ~(M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN);
-       }
-       writel_relaxed(val, se->base + SE_GENI_M_IRQ_EN);
+               if (val != val_old)
+                       writel_relaxed(val, se->base + SE_GENI_M_IRQ_EN);
 
-       val = readl_relaxed(se->base + SE_GENI_S_IRQ_EN);
-       if (proto != GENI_SE_UART)
+               val_old = val = readl_relaxed(se->base + SE_GENI_S_IRQ_EN);
                val &= ~S_CMD_DONE_EN;
-       writel_relaxed(val, se->base + SE_GENI_S_IRQ_EN);
+               if (val != val_old)
+                       writel_relaxed(val, se->base + SE_GENI_S_IRQ_EN);
+       }
 
-       val = readl_relaxed(se->base + SE_GENI_DMA_MODE_EN);
+       val_old = val = readl_relaxed(se->base + SE_GENI_DMA_MODE_EN);
        val |= GENI_DMA_MODE_EN;
-       writel_relaxed(val, se->base + SE_GENI_DMA_MODE_EN);
+       if (val != val_old)
+               writel_relaxed(val, se->base + SE_GENI_DMA_MODE_EN);
 }
 
 /**