ARM: dts: qcom: use defines for interrupts

Replace hard-coded interrupt parts (GIC, flags) with standard defines
for readability.  No changes in resulting DTBs.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Link: https://lore.kernel.org/r/20231205153317.346109-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>

diff --git a/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi
index 3faf57035d544d32d1ad4602a0c79f3e753bdc8a..656fecabefb96268c7041a716f99c9af1810be90 100644 (file)
--- a/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi
+++ b/arch/arm/boot/dts/qcom/qcom-apq8064.dtsi
@@ -190,7 +190,7 @@
 
        cpu-pmu {
                compatible = "qcom,krait-pmu";
-               interrupts = <1 10 0x304>;
+               interrupts = <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
        };
 
        clocks {
@@ -244,7 +244,7 @@
 
                modem_smsm: modem@1 {
                        reg = <1>;
-                       interrupts = <0 38 IRQ_TYPE_EDGE_RISING>;
+                       interrupts = <GIC_SPI 38 IRQ_TYPE_EDGE_RISING>;
 
                        interrupt-controller;
                        #interrupt-cells = <2>;
@@ -252,7 +252,7 @@
 
                q6_smsm: q6@2 {
                        reg = <2>;
-                       interrupts = <0 89 IRQ_TYPE_EDGE_RISING>;
+                       interrupts = <GIC_SPI 89 IRQ_TYPE_EDGE_RISING>;
 
                        interrupt-controller;
                        #interrupt-cells = <2>;
@@ -260,7 +260,7 @@
 
                wcnss_smsm: wcnss@3 {
                        reg = <3>;
-                       interrupts = <0 204 IRQ_TYPE_EDGE_RISING>;
+                       interrupts = <GIC_SPI 204 IRQ_TYPE_EDGE_RISING>;
 
                        interrupt-controller;
                        #interrupt-cells = <2>;
@@ -268,7 +268,7 @@
 
                dsps_smsm: dsps@4 {
                        reg = <4>;
-                       interrupts = <0 137 IRQ_TYPE_EDGE_RISING>;
+                       interrupts = <GIC_SPI 137 IRQ_TYPE_EDGE_RISING>;
 
                        interrupt-controller;
                        #interrupt-cells = <2>;
@@ -299,7 +299,7 @@
                        #gpio-cells = <2>;
                        interrupt-controller;
                        #interrupt-cells = <2>;
-                       interrupts = <0 16 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
 
                        pinctrl-names = "default";
                        pinctrl-0 = <&ps_hold>;
@@ -321,9 +321,9 @@
                timer@200a000 {
                        compatible = "qcom,kpss-wdt-apq8064", "qcom,kpss-timer",
                                     "qcom,msm-timer";
-                       interrupts = <1 1 0x301>,
-                                    <1 2 0x301>,
-                                    <1 3 0x301>;
+                       interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>,
+                                    <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>,
+                                    <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>;
                        reg = <0x0200a000 0x100>;
                        clock-frequency = <27000000>;
                        cpu-offset = <0x80000>;
@@ -411,7 +411,7 @@
                                compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
                                reg = <0x12450000 0x100>,
                                      <0x12400000 0x03>;
-                               interrupts = <0 193 IRQ_TYPE_LEVEL_HIGH>;
+                               interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&gcc GSBI1_UART_CLK>, <&gcc GSBI1_H_CLK>;
                                clock-names = "core", "iface";
                                status = "disabled";
@@ -423,7 +423,7 @@
                                pinctrl-1 = <&i2c1_pins_sleep>;
                                pinctrl-names = "default", "sleep";
                                reg = <0x12460000 0x1000>;
-                               interrupts = <0 194 IRQ_TYPE_LEVEL_HIGH>;
+                               interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&gcc GSBI1_QUP_CLK>, <&gcc GSBI1_H_CLK>;
                                clock-names = "core", "iface";
                                #address-cells = <1>;
@@ -452,7 +452,7 @@
                                pinctrl-0 = <&i2c2_pins>;
                                pinctrl-1 = <&i2c2_pins_sleep>;
                                pinctrl-names = "default", "sleep";
-                               interrupts = <0 196 IRQ_TYPE_LEVEL_HIGH>;
+                               interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
                                clock-names = "core", "iface";
                                #address-cells = <1>;
@@ -539,7 +539,7 @@
                                compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
                                reg = <0x1a240000 0x100>,
                                      <0x1a200000 0x03>;
-                               interrupts = <0 154 IRQ_TYPE_LEVEL_HIGH>;
+                               interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
                                clock-names = "core", "iface";
                                status = "disabled";
@@ -548,7 +548,7 @@
                        gsbi5_spi: spi@1a280000 {
                                compatible = "qcom,spi-qup-v1.1.1";
                                reg = <0x1a280000 0x1000>;
-                               interrupts = <0 155 IRQ_TYPE_LEVEL_HIGH>;
+                               interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
                                pinctrl-0 = <&spi5_default>;
                                pinctrl-1 = <&spi5_sleep>;
                                pinctrl-names = "default", "sleep";
@@ -575,7 +575,7 @@
                                compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
                                reg = <0x16540000 0x100>,
                                      <0x16500000 0x03>;
-                               interrupts = <0 156 IRQ_TYPE_LEVEL_HIGH>;
+                               interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&gcc GSBI6_UART_CLK>, <&gcc GSBI6_H_CLK>;
                                clock-names = "core", "iface";
                                status = "disabled";
@@ -611,7 +611,7 @@
                                compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
                                reg = <0x16640000 0x1000>,
                                      <0x16600000 0x1000>;
-                               interrupts = <0 158 IRQ_TYPE_LEVEL_HIGH>;
+                               interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>;
                                clock-names = "core", "iface";
                                status = "disabled";
@@ -908,7 +908,7 @@
                sdcc3bam: dma-controller@12182000 {
                        compatible = "qcom,bam-v1.3.0";
                        reg = <0x12182000 0x8000>;
-                       interrupts = <0 96 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
                        clocks = <&gcc SDC3_H_CLK>;
                        clock-names = "bam_clk";
                        #dma-cells = <1>;
@@ -936,7 +936,7 @@
                sdcc4bam: dma-controller@121c2000 {
                        compatible = "qcom,bam-v1.3.0";
                        reg = <0x121c2000 0x8000>;
-                       interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
                        clocks = <&gcc SDC4_H_CLK>;
                        clock-names = "bam_clk";
                        #dma-cells = <1>;
@@ -965,7 +965,7 @@
                sdcc1bam: dma-controller@12402000 {
                        compatible = "qcom,bam-v1.3.0";
                        reg = <0x12402000 0x8000>;
-                       interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
                        clocks = <&gcc SDC1_H_CLK>;
                        clock-names = "bam_clk";
                        #dma-cells = <1>;

diff --git a/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi b/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi
index 7846248a200f76cd666fd715daebdb83a92007dd..3f0272a9ea4687758da25e3b8045bc54b0490eea 100644 (file)
--- a/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi
+++ b/arch/arm/boot/dts/qcom/qcom-ipq4019.dtsi
@@ -162,10 +162,10 @@
 
        timer {
                compatible = "arm,armv7-timer";
-               interrupts = <1 2 0xf08>,
-                            <1 3 0xf08>,
-                            <1 4 0xf08>,
-                            <1 1 0xf08>;
+               interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+                            <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+                            <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+                            <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
                clock-frequency = <48000000>;
                always-on;
        };

diff --git a/arch/arm/boot/dts/qcom/qcom-msm8660.dtsi b/arch/arm/boot/dts/qcom/qcom-msm8660.dtsi
index a7c245b9c8f973c27472196ffb7ddf76a1a17670..17188fe54617d16608d23009d03b93dcde093aa4 100644 (file)
--- a/arch/arm/boot/dts/qcom/qcom-msm8660.dtsi
+++ b/arch/arm/boot/dts/qcom/qcom-msm8660.dtsi
@@ -47,7 +47,7 @@
 
        cpu-pmu {
                compatible = "qcom,scorpion-mp-pmu";
-               interrupts = <1 9 0x304>;
+               interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
        };
 
        clocks {
@@ -89,9 +89,9 @@
 
                timer@2000000 {
                        compatible = "qcom,scss-timer", "qcom,msm-timer";
-                       interrupts = <1 0 0x301>,
-                                    <1 1 0x301>,
-                                    <1 2 0x301>;
+                       interrupts = <GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>,
+                                    <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>,
+                                    <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>;
                        reg = <0x02000000 0x100>;
                        clock-frequency = <27000000>,
                                          <32768>;
@@ -105,7 +105,7 @@
                        gpio-controller;
                        gpio-ranges = <&tlmm 0 0 173>;
                        #gpio-cells = <2>;
-                       interrupts = <0 16 0x4>;
+                       interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
                        interrupt-controller;
                        #interrupt-cells = <2>;
 
@@ -283,7 +283,7 @@
                                compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
                                reg = <0x19c40000 0x1000>,
                                      <0x19c00000 0x1000>;
-                               interrupts = <0 195 IRQ_TYPE_LEVEL_HIGH>;
+                               interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&gcc GSBI12_UART_CLK>, <&gcc GSBI12_H_CLK>;
                                clock-names = "core", "iface";
                                status = "disabled";
@@ -292,7 +292,7 @@
                        gsbi12_i2c: i2c@19c80000 {
                                compatible = "qcom,i2c-qup-v1.1.1";
                                reg = <0x19c80000 0x1000>;
-                               interrupts = <0 196 IRQ_TYPE_LEVEL_HIGH>;
+                               interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
                                clocks = <&gcc GSBI12_QUP_CLK>, <&gcc GSBI12_H_CLK>;
                                clock-names = "core", "iface";
                                #address-cells = <1>;

diff --git a/arch/arm/boot/dts/qcom/qcom-msm8974.dtsi b/arch/arm/boot/dts/qcom/qcom-msm8974.dtsi
index b1413983787c2e2f6a6c38fdad8d97937ec4d0d3..c02040be3f8b2e828fda6466531fecc4a98f3522 100644 (file)
--- a/arch/arm/boot/dts/qcom/qcom-msm8974.dtsi
+++ b/arch/arm/boot/dts/qcom/qcom-msm8974.dtsi
@@ -31,7 +31,7 @@
        cpus {
                #address-cells = <1>;
                #size-cells = <0>;
-               interrupts = <GIC_PPI 9 0xf04>;
+               interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 
                CPU0: cpu@0 {
                        compatible = "qcom,krait";
@@ -110,7 +110,7 @@
 
        pmu {
                compatible = "qcom,krait-pmu";
-               interrupts = <GIC_PPI 7 0xf04>;
+               interrupts = <GIC_PPI 7 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
        };
 
        rpm: remoteproc {
@@ -538,7 +538,7 @@
                        status = "disabled";
                        compatible = "qcom,i2c-qup-v2.1.1";
                        reg = <0xf9923000 0x1000>;
-                       interrupts = <0 95 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
                        clocks = <&gcc GCC_BLSP1_QUP1_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
                        clock-names = "core", "iface";
                        pinctrl-names = "default", "sleep";
@@ -566,7 +566,7 @@
                        status = "disabled";
                        compatible = "qcom,i2c-qup-v2.1.1";
                        reg = <0xf9925000 0x1000>;
-                       interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
                        clocks = <&gcc GCC_BLSP1_QUP3_I2C_APPS_CLK>, <&gcc GCC_BLSP1_AHB_CLK>;
                        clock-names = "core", "iface";
                        pinctrl-names = "default", "sleep";
@@ -666,7 +666,7 @@
                        status = "disabled";
                        compatible = "qcom,i2c-qup-v2.1.1";
                        reg = <0xf9968000 0x1000>;
-                       interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
                        clocks = <&gcc GCC_BLSP2_QUP6_I2C_APPS_CLK>, <&gcc GCC_BLSP2_AHB_CLK>;
                        clock-names = "core", "iface";
                        pinctrl-names = "default", "sleep";
@@ -2403,10 +2403,10 @@
 
        timer {
                compatible = "arm,armv7-timer";
-               interrupts = <GIC_PPI 2 0xf08>,
-                            <GIC_PPI 3 0xf08>,
-                            <GIC_PPI 4 0xf08>,
-                            <GIC_PPI 1 0xf08>;
+               interrupts = <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+                            <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+                            <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+                            <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
                clock-frequency = <19200000>;
        };
 };

diff --git a/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi b/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi
index 2045fc779f887030735f9310982bdef228f8a481..3e540c831cfb93b80beeb0969bf82b94dffe6b81 100644 (file)
--- a/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi
+++ b/arch/arm/boot/dts/qcom/qcom-sdx55.dtsi
@@ -727,57 +727,57 @@
 
                        frame@17821000 {
                                frame-number = <0>;
-                               interrupts = <GIC_SPI 7 0x4>,
-                                            <GIC_SPI 6 0x4>;
+                               interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
                                reg = <0x17821000 0x1000>,
                                      <0x17822000 0x1000>;
                        };
 
                        frame@17823000 {
                                frame-number = <1>;
-                               interrupts = <GIC_SPI 8 0x4>;
+                               interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
                                reg = <0x17823000 0x1000>;
                                status = "disabled";
                        };
 
                        frame@17824000 {
                                frame-number = <2>;
-                               interrupts = <GIC_SPI 9 0x4>;
+                               interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
                                reg = <0x17824000 0x1000>;
                                status = "disabled";
                        };
 
                        frame@17825000 {
                                frame-number = <3>;
-                               interrupts = <GIC_SPI 10 0x4>;
+                               interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
                                reg = <0x17825000 0x1000>;
                                status = "disabled";
                        };
 
                        frame@17826000 {
                                frame-number = <4>;
-                               interrupts = <GIC_SPI 11 0x4>;
+                               interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
                                reg = <0x17826000 0x1000>;
                                status = "disabled";
                        };
 
                        frame@17827000 {
                                frame-number = <5>;
-                               interrupts = <GIC_SPI 12 0x4>;
+                               interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
                                reg = <0x17827000 0x1000>;
                                status = "disabled";
                        };
 
                        frame@17828000 {
                                frame-number = <6>;
-                               interrupts = <GIC_SPI 13 0x4>;
+                               interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
                                reg = <0x17828000 0x1000>;
                                status = "disabled";
                        };
 
                        frame@17829000 {
                                frame-number = <7>;
-                               interrupts = <GIC_SPI 14 0x4>;
+                               interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
                                reg = <0x17829000 0x1000>;
                                status = "disabled";
                        };

diff --git a/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi
index 1835413cdd6530ca8fbbba0bd50100fbb85e2e7b..031358bb20afe8b1a20d975efd117ebf83ea2c5b 100644 (file)
--- a/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi
+++ b/arch/arm/boot/dts/qcom/qcom-sdx65.dtsi
@@ -667,57 +667,57 @@
 
                        frame@17821000 {
                                frame-number = <0>;
-                               interrupts = <GIC_SPI 7 0x4>,
-                                            <GIC_SPI 6 0x4>;
+                               interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
+                                            <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
                                reg = <0x17821000 0x1000>,
                                      <0x17822000 0x1000>;
                        };
 
                        frame@17823000 {
                                frame-number = <1>;
-                               interrupts = <GIC_SPI 8 0x4>;
+                               interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
                                reg = <0x17823000 0x1000>;
                                status = "disabled";
                        };
 
                        frame@17824000 {
                                frame-number = <2>;
-                               interrupts = <GIC_SPI 9 0x4>;
+                               interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
                                reg = <0x17824000 0x1000>;
                                status = "disabled";
                        };
 
                        frame@17825000 {
                                frame-number = <3>;
-                               interrupts = <GIC_SPI 10 0x4>;
+                               interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
                                reg = <0x17825000 0x1000>;
                                status = "disabled";
                        };
 
                        frame@17826000 {
                                frame-number = <4>;
-                               interrupts = <GIC_SPI 11 0x4>;
+                               interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
                                reg = <0x17826000 0x1000>;
                                status = "disabled";
                        };
 
                        frame@17827000 {
                                frame-number = <5>;
-                               interrupts = <GIC_SPI 12 0x4>;
+                               interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
                                reg = <0x17827000 0x1000>;
                                status = "disabled";
                        };
 
                        frame@17828000 {
                                frame-number = <6>;
-                               interrupts = <GIC_SPI 13 0x4>;
+                               interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
                                reg = <0x17828000 0x1000>;
                                status = "disabled";
                        };
 
                        frame@17829000 {
                                frame-number = <7>;
-                               interrupts = <GIC_SPI 14 0x4>;
+                               interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
                                reg = <0x17829000 0x1000>;
                                status = "disabled";
                        };
@@ -804,10 +804,10 @@
 
        timer {
                compatible = "arm,armv7-timer";
-               interrupts = <1 13 0xf08>,
-                       <1 12 0xf08>,
-                       <1 10 0xf08>,
-                       <1 11 0xf08>;
+               interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+                            <GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+                            <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
+                            <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
                clock-frequency = <19200000>;
        };
 };