ARM: dts: r8a77(43|9[013]): Add missing OPP properties for CPUs

The OPP properties, like "operating-points", should either be present
for all the CPUs of a cluster or none. If these are present only for a
subset of CPUs of a cluster then things will start falling apart as soon
as the CPUs are brought online in a different order. For example, this
will happen because the operating system looks for such properties in
the CPU node it is trying to bring up, so that it can create an OPP
table.

Add such missing properties.

Fix other missing properties (like, clock latency, voltage tolerance,
etc) as well to make it all work.

Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>

diff --git a/arch/arm/boot/dts/r8a7743.dtsi b/arch/arm/boot/dts/r8a7743.dtsi
index 142949d7066f3a65cafe3fd065d3043f0841e5d8..e4fb31c4f0ee29c26baf820b42a4b94992913ea1 100644 (file)
--- a/arch/arm/boot/dts/r8a7743.dtsi
+++ b/arch/arm/boot/dts/r8a7743.dtsi
@@ -98,8 +98,17 @@
                        reg = <1>;
                        clock-frequency = <1500000000>;
                        clocks = <&cpg CPG_CORE R8A7743_CLK_Z>;
+                       clock-latency = <300000>; /* 300 us */
                        power-domains = <&sysc R8A7743_PD_CA15_CPU1>;
                        next-level-cache = <&L2_CA15>;
+
+                       /* kHz - uV - OPPs unknown yet */
+                       operating-points = <1500000 1000000>,
+                                          <1312500 1000000>,
+                                          <1125000 1000000>,
+                                          < 937500 1000000>,
+                                          < 750000 1000000>,
+                                          < 375000 1000000>;
                };
 
                L2_CA15: cache-controller-0 {

diff --git a/arch/arm/boot/dts/r8a7790.dtsi b/arch/arm/boot/dts/r8a7790.dtsi
index 4d06b154bd7ebd9eaa07436e6235bdacd76289f9..c4324b1a2ec4c6c7cb69b166df7209322b52e903 100644 (file)
--- a/arch/arm/boot/dts/r8a7790.dtsi
+++ b/arch/arm/boot/dts/r8a7790.dtsi
@@ -79,12 +79,12 @@
                        compatible = "arm,cortex-a15";
                        reg = <0>;
                        clock-frequency = <1300000000>;
-                       voltage-tolerance = <1>; /* 1% */
                        clocks = <&cpg CPG_CORE R8A7790_CLK_Z>;
-                       clock-latency = <300000>; /* 300 us */
                        power-domains = <&sysc R8A7790_PD_CA15_CPU0>;
                        next-level-cache = <&L2_CA15>;
                        capacity-dmips-mhz = <1024>;
+                       voltage-tolerance = <1>; /* 1% */
+                       clock-latency = <300000>; /* 300 us */
 
                        /* kHz - uV - OPPs unknown yet */
                        operating-points = <1400000 1000000>,
@@ -104,6 +104,16 @@
                        power-domains = <&sysc R8A7790_PD_CA15_CPU1>;
                        next-level-cache = <&L2_CA15>;
                        capacity-dmips-mhz = <1024>;
+                       voltage-tolerance = <1>; /* 1% */
+                       clock-latency = <300000>; /* 300 us */
+
+                       /* kHz - uV - OPPs unknown yet */
+                       operating-points = <1400000 1000000>,
+                                          <1225000 1000000>,
+                                          <1050000 1000000>,
+                                          < 875000 1000000>,
+                                          < 700000 1000000>,
+                                          < 350000 1000000>;
                };
 
                cpu2: cpu@2 {
@@ -115,6 +125,16 @@
                        power-domains = <&sysc R8A7790_PD_CA15_CPU2>;
                        next-level-cache = <&L2_CA15>;
                        capacity-dmips-mhz = <1024>;
+                       voltage-tolerance = <1>; /* 1% */
+                       clock-latency = <300000>; /* 300 us */
+
+                       /* kHz - uV - OPPs unknown yet */
+                       operating-points = <1400000 1000000>,
+                                          <1225000 1000000>,
+                                          <1050000 1000000>,
+                                          < 875000 1000000>,
+                                          < 700000 1000000>,
+                                          < 350000 1000000>;
                };
 
                cpu3: cpu@3 {
@@ -126,6 +146,16 @@
                        power-domains = <&sysc R8A7790_PD_CA15_CPU3>;
                        next-level-cache = <&L2_CA15>;
                        capacity-dmips-mhz = <1024>;
+                       voltage-tolerance = <1>; /* 1% */
+                       clock-latency = <300000>; /* 300 us */
+
+                       /* kHz - uV - OPPs unknown yet */
+                       operating-points = <1400000 1000000>,
+                                          <1225000 1000000>,
+                                          <1050000 1000000>,
+                                          < 875000 1000000>,
+                                          < 700000 1000000>,
+                                          < 350000 1000000>;
                };
 
                cpu4: cpu@100 {

diff --git a/arch/arm/boot/dts/r8a7791.dtsi b/arch/arm/boot/dts/r8a7791.dtsi
index 6e1dd7ad7bd647e7db66c1db8947c1d9718957ce..d1d726a1364ad5c7c0a21794d261e10f97b353f0 100644 (file)
--- a/arch/arm/boot/dts/r8a7791.dtsi
+++ b/arch/arm/boot/dts/r8a7791.dtsi
@@ -78,11 +78,11 @@
                        compatible = "arm,cortex-a15";
                        reg = <0>;
                        clock-frequency = <1500000000>;
-                       voltage-tolerance = <1>; /* 1% */
                        clocks = <&cpg CPG_CORE R8A7791_CLK_Z>;
-                       clock-latency = <300000>; /* 300 us */
                        power-domains = <&sysc R8A7791_PD_CA15_CPU0>;
                        next-level-cache = <&L2_CA15>;
+                       voltage-tolerance = <1>; /* 1% */
+                       clock-latency = <300000>; /* 300 us */
 
                        /* kHz - uV - OPPs unknown yet */
                        operating-points = <1500000 1000000>,
@@ -101,6 +101,16 @@
                        clocks = <&cpg CPG_CORE R8A7791_CLK_Z>;
                        power-domains = <&sysc R8A7791_PD_CA15_CPU1>;
                        next-level-cache = <&L2_CA15>;
+                       voltage-tolerance = <1>; /* 1% */
+                       clock-latency = <300000>; /* 300 us */
+
+                       /* kHz - uV - OPPs unknown yet */
+                       operating-points = <1500000 1000000>,
+                                          <1312500 1000000>,
+                                          <1125000 1000000>,
+                                          < 937500 1000000>,
+                                          < 750000 1000000>,
+                                          < 375000 1000000>;
                };
 
                L2_CA15: cache-controller-0 {

diff --git a/arch/arm/boot/dts/r8a7793.dtsi b/arch/arm/boot/dts/r8a7793.dtsi
index 4abecfc0ca98c48346114b5f44600e795182aedb..1e6439b85a6bab8265c46f4bee9a2ebcd1e7782b 100644 (file)
--- a/arch/arm/boot/dts/r8a7793.dtsi
+++ b/arch/arm/boot/dts/r8a7793.dtsi
@@ -70,10 +70,10 @@
                        compatible = "arm,cortex-a15";
                        reg = <0>;
                        clock-frequency = <1500000000>;
-                       voltage-tolerance = <1>; /* 1% */
                        clocks = <&cpg CPG_CORE R8A7793_CLK_Z>;
-                       clock-latency = <300000>; /* 300 us */
                        power-domains = <&sysc R8A7793_PD_CA15_CPU0>;
+                       voltage-tolerance = <1>; /* 1% */
+                       clock-latency = <300000>; /* 300 us */
 
                        /* kHz - uV - OPPs unknown yet */
                        operating-points = <1500000 1000000>,
@@ -92,6 +92,17 @@
                        clock-frequency = <1500000000>;
                        clocks = <&cpg CPG_CORE R8A7793_CLK_Z>;
                        power-domains = <&sysc R8A7793_PD_CA15_CPU1>;
+                       voltage-tolerance = <1>; /* 1% */
+                       clock-latency = <300000>; /* 300 us */
+
+                       /* kHz - uV - OPPs unknown yet */
+                       operating-points = <1500000 1000000>,
+                                          <1312500 1000000>,
+                                          <1125000 1000000>,
+                                          < 937500 1000000>,
+                                          < 750000 1000000>,
+                                          < 375000 1000000>;
+                       next-level-cache = <&L2_CA15>;
                };
 
                L2_CA15: cache-controller-0 {