riscv: dts: starfive: convert isa detection to new properties

Convert the jh7100 and jh7110 devicetrees to use the new properties
"riscv,isa-base" & "riscv,isa-extensions".
For compatibility with other projects, "riscv,isa" remains.

Signed-off-by: Conor Dooley <conor.dooley@microchip.com>

diff --git a/arch/riscv/boot/dts/starfive/jh7100.dtsi b/arch/riscv/boot/dts/starfive/jh7100.dtsi
index 35ab54fb235fa27ea34bbf706eb87361710d80c6..e68cafe7545f75e5dfbe1147574a0d5f6c3a8a23 100644 (file)
--- a/arch/riscv/boot/dts/starfive/jh7100.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7100.dtsi
@@ -33,6 +33,9 @@
                        i-tlb-size = <32>;
                        mmu-type = "riscv,sv39";
                        riscv,isa = "rv64imafdc";
+                       riscv,isa-base = "rv64i";
+                       riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
+                                              "zifencei", "zihpm";
                        tlb-split;
 
                        cpu0_intc: interrupt-controller {
@@ -58,6 +61,9 @@
                        i-tlb-size = <32>;
                        mmu-type = "riscv,sv39";
                        riscv,isa = "rv64imafdc";
+                       riscv,isa-base = "rv64i";
+                       riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
+                                              "zifencei", "zihpm";
                        tlb-split;
 
                        cpu1_intc: interrupt-controller {

diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
index 9f31dec57c0d19c5eec940d227162bf96ce63ff2..45213cdf50dc75a9fa6610710a4d0cbe58b44c51 100644 (file)
--- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
@@ -28,6 +28,9 @@
                        i-cache-size = <16384>;
                        next-level-cache = <&ccache>;
                        riscv,isa = "rv64imac_zba_zbb";
+                       riscv,isa-base = "rv64i";
+                       riscv,isa-extensions = "i", "m", "a", "c", "zba", "zbb", "zicntr", "zicsr",
+                                              "zifencei", "zihpm";
                        status = "disabled";
 
                        cpu0_intc: interrupt-controller {
@@ -54,6 +57,9 @@
                        mmu-type = "riscv,sv39";
                        next-level-cache = <&ccache>;
                        riscv,isa = "rv64imafdc_zba_zbb";
+                       riscv,isa-base = "rv64i";
+                       riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zba", "zbb", "zicntr",
+                                              "zicsr", "zifencei", "zihpm";
                        tlb-split;
                        operating-points-v2 = <&cpu_opp>;
                        clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>;
@@ -84,6 +90,9 @@
                        mmu-type = "riscv,sv39";
                        next-level-cache = <&ccache>;
                        riscv,isa = "rv64imafdc_zba_zbb";
+                       riscv,isa-base = "rv64i";
+                       riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zba", "zbb", "zicntr",
+                                              "zicsr", "zifencei", "zihpm";
                        tlb-split;
                        operating-points-v2 = <&cpu_opp>;
                        clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>;
@@ -114,6 +123,9 @@
                        mmu-type = "riscv,sv39";
                        next-level-cache = <&ccache>;
                        riscv,isa = "rv64imafdc_zba_zbb";
+                       riscv,isa-base = "rv64i";
+                       riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zba", "zbb", "zicntr",
+                                              "zicsr", "zifencei", "zihpm";
                        tlb-split;
                        operating-points-v2 = <&cpu_opp>;
                        clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>;
@@ -144,6 +156,9 @@
                        mmu-type = "riscv,sv39";
                        next-level-cache = <&ccache>;
                        riscv,isa = "rv64imafdc_zba_zbb";
+                       riscv,isa-base = "rv64i";
+                       riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zba", "zbb", "zicntr",
+                                              "zicsr", "zifencei", "zihpm";
                        tlb-split;
                        operating-points-v2 = <&cpu_opp>;
                        clocks = <&syscrg JH7110_SYSCLK_CPU_CORE>;