media: st-mipid02: add support of pixel clock polarity

Add support of pixel clock polarity.

Signed-off-by: Hugues Fruchet <hugues.fruchet@foss.st.com>
Reviewed-by: Benjamin Mugnier <benjamin.mugnier@foss.st.com>
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab@kernel.org>

diff --git a/drivers/media/i2c/st-mipid02.c b/drivers/media/i2c/st-mipid02.c
index ef976d085d72c7eefc374e7851ff20301fbff45d..59b48026c752ac41c4857537a92bb68daf75a3ea 100644 (file)
--- a/drivers/media/i2c/st-mipid02.c
+++ b/drivers/media/i2c/st-mipid02.c
@@ -50,6 +50,7 @@
 /* Bits definition for MIPID02_MODE_REG2 */
 #define MODE_HSYNC_ACTIVE_HIGH                         BIT(1)
 #define MODE_VSYNC_ACTIVE_HIGH                         BIT(2)
+#define MODE_PCLK_SAMPLE_RISING                                BIT(3)
 /* Bits definition for MIPID02_DATA_SELECTION_CTRL */
 #define SELECTION_MANUAL_DATA                          BIT(2)
 #define SELECTION_MANUAL_WIDTH                         BIT(3)
@@ -494,6 +495,8 @@ static int mipid02_configure_from_tx(struct mipid02_dev *bridge)
                bridge->r.mode_reg2 |= MODE_HSYNC_ACTIVE_HIGH;
        if (ep->bus.parallel.flags & V4L2_MBUS_VSYNC_ACTIVE_HIGH)
                bridge->r.mode_reg2 |= MODE_VSYNC_ACTIVE_HIGH;
+       if (ep->bus.parallel.flags & V4L2_MBUS_PCLK_SAMPLE_RISING)
+               bridge->r.mode_reg2 |= MODE_PCLK_SAMPLE_RISING;
 
        return 0;
 }