drm/xe/xelpg: Recognize graphics version 12.74 as Xe_LPG

Graphics version 12.74 (which is technically called "Xe_LPG+") should be
handled the same as versions Xe_LPG 12.70/12.71 by the KMD.  Only the
workaround lists (handled in the next patch) will be a bit different.

Bspec: 55420
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Dnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com>
Reviewed-by: Matt Atwood <matthew.s.atwood@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240229070806.3402641-2-dnyaneshwar.bhadane@intel.com

diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
index 557f2d88a8c1ed7bce5698433be1f0824121be5e..c401d4890386d9ca78ca3d9cdefc957b0f2c5b45 100644 (file)
--- a/drivers/gpu/drm/xe/xe_pci.c
+++ b/drivers/gpu/drm/xe/xe_pci.c
@@ -343,6 +343,7 @@ __diag_pop();
 static const struct gmdid_map graphics_ip_map[] = {
        { 1270, &graphics_xelpg },
        { 1271, &graphics_xelpg },
+       { 1274, &graphics_xelpg },      /* Xe_LPG+ */
        { 2004, &graphics_xe2 },
 };
 

diff --git a/drivers/gpu/drm/xe/xe_tuning.c b/drivers/gpu/drm/xe/xe_tuning.c
index 5c83c75bc4978dccad0f9d8bc242a687a3739106..bb6db2817ada4d18514782252ba533933cc2dd04 100644 (file)
--- a/drivers/gpu/drm/xe/xe_tuning.c
+++ b/drivers/gpu/drm/xe/xe_tuning.c
@@ -50,7 +50,7 @@ static const struct xe_rtp_entry_sr gt_tunings[] = {
 
 static const struct xe_rtp_entry_sr engine_tunings[] = {
        { XE_RTP_NAME("Tuning: Set Indirect State Override"),
-         XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1271),
+         XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1274),
                       ENGINE_CLASS(RENDER)),
          XE_RTP_ACTIONS(SET(SAMPLER_MODE, INDIRECT_STATE_BASE_ADDR_OVERRIDE))
        },
@@ -88,7 +88,7 @@ static const struct xe_rtp_entry_sr lrc_tunings[] = {
        /* Xe_LPG */
 
        { XE_RTP_NAME("Tuning: L3 cache"),
-         XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1271), ENGINE_CLASS(RENDER)),
+         XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1274), ENGINE_CLASS(RENDER)),
          XE_RTP_ACTIONS(FIELD_SET(XEHP_L3SQCREG5, L3_PWM_TIMER_INIT_VAL_MASK,
                                   REG_FIELD_PREP(L3_PWM_TIMER_INIT_VAL_MASK, 0x7f)))
        },