drm/amd/display: Link training TPS1 workaround

[Why]
Previously implemented early_cr_pattern was link level but the whole
asic should be affected.

[How]
 - change old link flag to dc level
 - new bit in dc->work_arounds set by DM

Signed-off-by: Martin Leung <martin.leung@amd.com>
Reviewed-by: Joshua Aberback <Joshua.Aberback@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
index 8de9d6f9a477f45ad729461c9841a887a7b338d1..93127bc90f3cd28e041d85dd2dacef5b61026508 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
@@ -973,7 +973,7 @@ static enum link_training_result perform_clock_recovery_sequence(
        retries_cr = 0;
        retry_count = 0;
 
-       if (!link->wa_flags.dp_early_cr_pattern)
+       if (!link->ctx->dc->work_arounds.lt_early_cr_pattern)
                dp_set_hw_training_pattern(link, tr_pattern, offset);
 
        /* najeeb - The synaptics MST hub can put the LT in
@@ -1446,11 +1446,11 @@ enum link_training_result dc_link_dp_perform_link_training(
                        &link->preferred_training_settings,
                        &lt_settings);
 
-       if (link->wa_flags.dp_early_cr_pattern)
-               start_clock_recovery_pattern_early(link, &lt_settings, DPRX);
-
        /* 1. set link rate, lane count and spread. */
-       dpcd_set_link_settings(link, &lt_settings);
+       if (link->ctx->dc->work_arounds.lt_early_cr_pattern)
+               start_clock_recovery_pattern_early(link, &lt_settings, DPRX);
+       else
+               dpcd_set_link_settings(link, &lt_settings);
 
        if (link->preferred_training_settings.fec_enable != NULL)
                fec_enable = *link->preferred_training_settings.fec_enable;
@@ -1669,11 +1669,11 @@ enum link_training_result dc_link_dp_sync_lt_attempt(
        dp_set_panel_mode(link, panel_mode);
 
        /* Attempt to train with given link training settings */
-       if (link->wa_flags.dp_early_cr_pattern)
-               start_clock_recovery_pattern_early(link, &lt_settings, DPRX);
-
        /* Set link rate, lane count and spread. */
-       dpcd_set_link_settings(link, &lt_settings);
+       if (link->ctx->dc->work_arounds.lt_early_cr_pattern)
+               start_clock_recovery_pattern_early(link, &lt_settings, DPRX);
+       else
+               dpcd_set_link_settings(link, &lt_settings);
 
        /* 2. perform link training (set link training done
         *  to false is done as well)

diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h
index b3f6311d3564fa2c919b058806dbbbad8b27c5e0..72298520a30360d3e5f73242484f41d5f112ceab 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dc.h
+++ b/drivers/gpu/drm/amd/display/dc/dc.h
@@ -126,6 +126,7 @@ struct dc_bug_wa {
        bool no_connect_phy_config;
        bool dedcn20_305_wa;
        bool skip_clock_update;
+       bool lt_early_cr_pattern;
 };
 
 struct dc_dcc_surface_param {

diff --git a/drivers/gpu/drm/amd/display/dc/dc_link.h b/drivers/gpu/drm/amd/display/dc/dc_link.h
index 6344de3ca9791b47dde345daf87518f7a1bf4e4e..5f341e960506f8bb906d297cc9c7c9da7be1ce15 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dc_link.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_link.h
@@ -135,7 +135,6 @@ struct dc_link {
                bool dp_keep_receiver_powered;
                bool dp_skip_DID2;
                bool dp_skip_reset_segment;
-               bool dp_early_cr_pattern;
        } wa_flags;
        struct link_mst_stream_allocation_table mst_stream_alloc_table;