PCI: Mark Cavium CN8xxx to avoid bus reset
authorDavid Daney <david.daney@cavium.com>
Fri, 8 Sep 2017 08:10:32 +0000 (10:10 +0200)
committerBjorn Helgaas <bhelgaas@google.com>
Wed, 11 Oct 2017 18:23:35 +0000 (13:23 -0500)
Root ports of cn8xxx do not function after bus reset when used with some
e1000e and LSI HBA devices.  Add a quirk to prevent bus reset on these root
ports.

Signed-off-by: David Daney <david.daney@cavium.com>
[jglauber@cavium.com: fixed typo and whitespaces]
Signed-off-by: Jan Glauber <jglauber@cavium.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Alex Williamson <alex.williamson@redhat.com>
drivers/pci/quirks.c

index a4d33619a7bb67157f128f0009a58f9d21c7c727..8c2fd3dc8df631ddc98dacf5d444753071e81654 100644 (file)
@@ -3365,6 +3365,13 @@ DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0032, quirk_no_bus_reset);
 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x003c, quirk_no_bus_reset);
 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0033, quirk_no_bus_reset);
 
+/*
+ * Root port on some Cavium CN8xxx chips do not successfully complete a bus
+ * reset when used with certain child devices.  After the reset, config
+ * accesses to the child may fail.
+ */
+DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CAVIUM, 0xa100, quirk_no_bus_reset);
+
 static void quirk_no_pm_reset(struct pci_dev *dev)
 {
        /*