[CLKID_SPICC1_SCLK_SEL]         = &g12a_spicc1_sclk_sel.hw,
                [CLKID_SPICC1_SCLK_DIV]         = &g12a_spicc1_sclk_div.hw,
                [CLKID_SPICC1_SCLK]             = &g12a_spicc1_sclk.hw,
+               [CLKID_NNA_AXI_CLK_SEL]         = &sm1_nna_axi_clk_sel.hw,
+               [CLKID_NNA_AXI_CLK_DIV]         = &sm1_nna_axi_clk_div.hw,
+               [CLKID_NNA_AXI_CLK]             = &sm1_nna_axi_clk.hw,
+               [CLKID_NNA_CORE_CLK_SEL]        = &sm1_nna_core_clk_sel.hw,
+               [CLKID_NNA_CORE_CLK_DIV]        = &sm1_nna_core_clk_div.hw,
+               [CLKID_NNA_CORE_CLK]            = &sm1_nna_core_clk.hw,
                [CLKID_MIPI_DSI_PXCLK_SEL]      = &g12a_mipi_dsi_pxclk_sel.hw,
                [CLKID_MIPI_DSI_PXCLK_DIV]      = &g12a_mipi_dsi_pxclk_div.hw,
                [CLKID_MIPI_DSI_PXCLK]          = &g12a_mipi_dsi_pxclk.hw,